Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

Page: 109 / 308

PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 109
14. Digital Clocks
This chapter discusses the Digital Clocks and their associated registers. It serves as an overview of the clocking options
available in the PSoC devices. For detailed information on specific oscillators, see the individual oscillator chapters in the sec-
tion called
PSoC Core on page 23 . For a complete table of the digital clock registers, refer to the System Resources Register
Summary on page 106 . For a quick reference of all PSoC registers in address order, refer to the Register Reference chapter
on page 187 .
14.1 Architectural Description
The PSoC M8C core has a large number of clock sources
that increase the flexibility of the PSoC device, as listed in
Table 14-1 and illustrated in Figure 14-1 .
14.1.1 Internal Main Oscillator
The Internal Main Oscillator (IMO) is the foundation upon
which almost all other clock sources in the PSoC device are
based. The default mode of the IMO creates a 12 MHz refer-
ence clock that is used by many other circuits in the device.
The PSoC device has an option to replace the IMO with an
externally supplied clock that becomes the base for all of the
clocks the IMO normally serves. The internal base clock net
is called SYSCLK and is driven by either the IMO or an
external clock (EXTCLK).
Whether the external clock or the internal main oscillator is
selected, all device functions are clocked from a derivative
of SYSCLK or are resynchronized to SYSCLK. All external
asynchronous signals and the internal low speed oscillator
are resynchronized to SYSCLK for use in the digital blocks.
The IMO frequency can be adjusted to other frequencies
besides 12 MHz. See the
Architectural Description on
page 63 , in the Internal Main Oscillator chapter, for more
information.
The IMO is discussed in detail in the chapter Internal Main
Oscillator (IMO) on page 63 .
Table 14-1. System Clocking Signals and Definitions
Signal Definition
SYSCLK
Either the direct output of the Internal Main Oscillator or the
direct input of the EXTCLK pin while in external clocking
mode.
CPUCLK
SYSCLK is divided down to one of eight possible frequencies
to create CPUCLK, which determines the speed of the M8C.
See the
OSC_CR0 Register in the Register Definitions sec-
tion of this chapter.
CLK32K
The Internal Low Speed Oscillators output. See the
OSC_CR0 Register in the Register Definitions section of this
chapter.
CLKIM0
The internally generated clock from the IMO. By default, this
clock drives SYSCLK; however, an external clock may be
used by enabling EXTCLK mode. The IMO can be set to var-
ious frequencies; the default is 12 MHz.
SLEEP
One of four sleep intervals may be selected from 1.95 ms to 1
second. See the
OSC_CR0 Register in the Register Defini-
tions section of this chapter.
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