Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

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PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 23
Section B: PSoC Core
The PSoC Core section discusses the core components of a PSoC device with a base part number of CY8CTMG20x or
CY8CTST200 and the registers associated with those components. The core section covers the heart of the PSoC device,
which includes the M8C
microcontroller ; SROM, interrupt controller, GPIO, and SRAM paging; multiple clock sources such
as IMO and ILO; and sleep and watchdog functionality. This section includes these chapters:
■
CPU Core (M8C) on page 27 .
■
Supervisory ROM (SROM) on page 33 .
■
RAM Paging on page 39 .
■
Interrupt Controller on page 45 .
■
General Purpose I/O (GPIO) on page 55 .
■
Internal Main Oscillator (IMO) on page 63 .
■
Internal Low Speed Oscillator (ILO) on page 67 .
■
External Crystal Oscillator (ECO), on page 69
■
Sleep and Watchdog on page 73 .
Top-Level Core Architecture
This figure displays the top level architecture of the PSoC core. Each component of the figure is discussed at length in this
section.
PSoC Core Block Diagram
1K, 2K
SRAM
Interrupt
Controller
Sleep and
Watchdog
Multiple Clock Sources
Internal Low Speed Oscillator (ILO)
6/12/24 MHz Internal Main Oscillator (IMO)
CORE
CPU Core (M8C)
Supervisory ROM (SROM)
8K, 16K, 32K Flash
Nonvolatile Memory
SYSTEM BUS
Port 3 Port 2 Port 1 Port 0
1.8/2.5/3V
LDO
PWRSYS
(Regulator)
Port 4
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