Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

Page: 101 / 308

PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 101
13. Comparators
This chapter explains the Comparators for the CY8CTMG20x and CY8CTST200 PSoC devices and their associated regis-
ters. For a complete table of the comparator registers, refer to the
TrueTouch Register Summary on page 84 . For a quick ref-
erence of all registers in address order, refer to the Register Reference chapter on page 187 .
13.1 Architectural Description
The CY8CTMG20x and CY8CTST200 PSoC devices contain two comparators designed to support capacitive sensing or
other general purpose uses.
Figure 13-1 shows a block diagram of the comparator system.
Figure 13-1. Comparators Block Diagram
LUT
CMP1
To: Cap Sense Logic,
CMP0 LUT
Reg Write
AMuxBus
Reserved
P0[1]
P0[3]
VREF
RefLo
RefHi
Reserved
2
COMP1
Enable, Range
(CMP_CR0)
INN1[1:0]
(CMP_MUX)
Comparator Analog System
CMP1D
(CMP_RDC)
INP1[1:0]
(CMP_MUX)
A
B
LATCH
S
R
I/O Read
I/O Read
LUT1[3:0]
(CMP_LUT)
CMP1L
(CMP_RDC)
CMP1O To: Pin Outputs
CDS1
(CMP_CR1)
CRST1
(CMP_CR1)
CPIN1
(CMP_CR1)
LUT
CMP0
To: Cap Sense Logic,
CMP1 LUT
Reg Write
AMuxBus
Reserved
P0[1]
P0[3]
VREF
RefLo
RefHi
Reserved
2
COMP0
Enable, Range
(CMP_CR0)
INN0[1:0]
(CMP_MUX)
CMP0D
(CMP_RDC)
INP0[1:0]
(CMP_MUX)
A
B
LATCH
S
R
I/O Read
I/O Read
LUT0[3:0]
(CMP_LUT)
CMP0L
(CMP_RDC)
CMP0O To: Pin Outputs
CDS0
(CMP_CR1)
CRST0
(CMP_CR1)
CPIN0 (CMP_CR1)
CMP0 LUT
CMP1 LUT
CMP1
CINT1
CMP0
CINT0
To: Analog
Interrupt
LPF
LPFilt[1:0]
(CS_CR3)
LPF_EN[1]
(CS_CR3)
LPF_EN[0]
(CS_CR3)
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