Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

Page: 261 / 308

PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 261
SPI_CFG
1,29h
21.4.3 SPI_CFG
SPI Configuration Register
This register is used to configure the SPI.
Do not change the values in this register while the block is enabled. For additional information, refer to the Register Defini-
tions on page 147 in the SPI chapter.
7:5 Clock Sel [2:0] SYSCLK in Master mode.
000b
/ 2
001b / 4
010b / 8
011b / 16
100b / 32
101b / 64
110b / 128
111b / 256
4 Bypass Bypass Synchronization.
0
All pin inputs are doubled and synchronized.
1 Input synchronization is bypassed.
3 SS_ Slave Select in Slave mode.
0
Slave selected.
1 Slave not selected.
2 SS_EN_ Internal Slave Select Enable.
0
Slave selection determined from SS_ bit.
1 Slave selection determined from external SS_ pin.
1 Int Sel Interrupt Select.
0
Interrupt on TX Reg Empty.
1 Interrupt on SPI Complete.
0 Slave 0 Operates as a master.
1 Operates as a slave.
Individual Register Names and Addresses:
1,29h
SPI_CFG : 1,29h
7 6 5 4 3 2 1 0
Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0
Bit Name Clock Sel [2:0] Bypass SS_ SS_EN_ Int Sel Slave
Bit Name Description
[+] Feedback