Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

Page: 147 / 308

PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 147
SPI
18.1.3.2 Block Interrupt
The SPIS block has a selection of two interrupt sources:
Interrupt on TX Reg Empty (default) or interrupt on SPI
Complete (same selection as the SPIM). Mode bit 1 in the
Function register controls the selection.
If SPI Complete is selected as the block interrupt, the Con-
trol register must still be read in the interrupt routine so that
this status bit is cleared; otherwise, no subsequent inter-
rupts are generated.
18.1.4 Input Synchronization
All pin inputs are double synchronized to SYSCLK by
default. Synchronization can be bypassed by setting the
BYPS bit in the SPI_CFG register.
18.2 Register Definitions
The following registers are associated with the SPI and are listed in address order. The register descriptions have an associ-
ated register table showing the bit structure for that register. For a complete table of SPI registers, refer to the
Summary Table
of the System Resource Registers on page 106 .
Data Registers
18.2.1 SPI_TXR Register
The SPI Transmit Data Register (SPI_TXR) is the SPI’s
transmit data register. Bits 7 to 0: Data[7:0]. These bits encompass the SPI
Transmit register. They are discussed by function type in
Table 18-2 and Table 18-3 .
For additional information, refer to the SPI_TXR register on
page 190 .
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
0,29h SPI_TXR Data[7:0] W : 00
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