8
Interfaces ...................................................................................................................................................... 34
8.1 Programmable I/O Ports, PIO .............................................................................................................. 34
8.2 Analogue I/O Ports, AIO ...................................................................................................................... 34
8.3 LED Drivers ......................................................................................................................................... 34
9
Audio Interface .............................................................................................................................................. 36
9.1 Audio Input and Output ........................................................................................................................ 37
9.2 Audio Codec Interface ......................................................................................................................... 37
9.2.1
Audio Codec Block Diagram .................................................................................................. 38
9.2.2
ADC ........................................................................................................................................ 38
9.2.3
ADC Sample Rate Selection .................................................................................................. 38
9.2.4
ADC Audio Input Gain ............................................................................................................ 39
9.2.5
ADC Pre-amplifier and ADC Analogue Gain .......................................................................... 39
9.2.6
ADC Digital Gain .................................................................................................................... 39
9.2.7
ADC Digital IIR Filter .............................................................................................................. 40
9.2.8
DAC ........................................................................................................................................ 40
9.2.9
DAC Sample Rate Selection .................................................................................................. 40
9.2.10 DAC Digital Gain .................................................................................................................... 40
9.2.11 DAC Analogue Gain ............................................................................................................... 41
9.2.12 DAC Digital FIR Filter ............................................................................................................. 41
9.2.13 Microphone Input ................................................................................................................... 42
9.2.14 Digital Microphone Inputs ....................................................................................................... 43
9.2.15 Line Input ............................................................................................................................... 43
9.2.16 Output Stage .......................................................................................................................... 44
9.2.17 Mono Operation ..................................................................................................................... 44
9.2.18 Side Tone ............................................................................................................................... 45
9.2.19 Integrated Digital IIR Filter ..................................................................................................... 46
9.3 PCM1 Interface .................................................................................................................................... 47
9.3.1
PCM Interface Master/Slave .................................................................................................. 48
9.3.2
Long Frame Sync ................................................................................................................... 49
9.3.3
Short Frame Sync .................................................................................................................. 49
9.3.4
Multi-slot Operation ................................................................................................................ 49
9.3.5
GCI Interface .......................................................................................................................... 50
9.3.6
Slots and Sample Formats ..................................................................................................... 50
9.3.7
Additional Features ................................................................................................................ 51
9.3.8
PCM Timing Information ........................................................................................................ 52
9.3.9
PCM_CLK and PCM_SYNC Generation ................................................................................ 55
9.3.10 PCM Configuration ................................................................................................................. 56
9.4 Digital Audio Interface (I²S) .................................................................................................................. 56
10
Power Control and Regulation ...................................................................................................................... 60
10.1 1.8V Switch-mode Regulator ............................................................................................................... 63
10.2 1.35V Switch-mode Regulator ............................................................................................................. 63
10.3 1.8V and 1.35V Switch-mode Regulators Combined .......................................................................... 64
10.4 Bypass LDO Linear Regulator ............................................................................................................. 65
10.5 Low-voltage VDD_DIG Linear Regulator ............................................................................................. 66
10.6 Low-voltage VDD_AUX Linear Regulator ............................................................................................ 66
10.7 Low-voltage VDD_ANA Linear Regulator ............................................................................................ 66
10.8 Voltage Regulator Enable .................................................................................................................... 66
Advance Information
This material is subject to CSR's non-disclosure agreement
© Cambridge Silicon Radio Limited 2011
Page 8 of 110
CS-209182-DSP1
CSR8640 BGA
Data Sheet
