9.2.1
Audio Codec Block Diagram
G
-TW
-0007452
.3.2
Digital Mic
Digital Mic
Digital Codec
16
Input C
Input B
Input A
High-quality ADC
High-quality ADC
Data
Mu
x
16
16
Data
MIC_BP
MIC_BN
MIC_AP
MIC_AN
Clock
Clock
PIO[ODD]
PIO[ODD]
Digital Codec
Digital Codec
Note:
L/R pins on digital microphones
pulled up or down on the PCB
Stereo Audio and Voice Band Output
High-quality DAC
Low-pass Filter
SPKR_LN
SPKR_LP
16
High-quality DAC
SPKR_RN
SPKR_RP
16
Digital Circuitry
Stereo Audio, Voice Band and Digital Microphone Input
PIO[EVEN]
PIO[EVEN]
Low-pass Filter
Digital MIC Interface
Digital MIC Interface
Figure 9.2: Audio Codec Input and Output Stages
The CSR8640 BGA audio codec uses a fully differential architecture in the analogue signal path, which results in
low noise sensitivity and good power supply rejection while effectively doubling the signal amplitude. It operates from
a dual power supply, VDD_AUDIO for the audio circuits and VDD_AUDIO_DRV for the audio driver circuits.
9.2.2
ADC
Figure 9.2 shows the CSR8640 BGA consists of 2 high-quality ADCs:
■
Each ADC has a second-order Sigma-Delta converter.
■
Each ADC is a separate channel with identical functionality.
■
There are 2 gain stages for each channel, 1 of which is an analogue gain stage and the other is a digital
gain stage, see Section 9.2.4.
9.2.3
ADC Sample Rate Selection
Each ADC supports the following pre-defined sample rates, although other rates are programmable, e.g. 40kHz:
■
8kHz
■
11.025kHz
■
16kHz
■
22.050kHz
■
24kHz
■
32kHz
■
44.1kHz
■
48kHz
Advance Information
This material is subject to CSR's non-disclosure agreement
© Cambridge Silicon Radio Limited 2011
Page 38 of 110
CS-209182-DSP1
CSR8640 BGA
Data Sheet
