G
-TW
-0
000221
.3.2
LONG_PCM_SYNC
Or
SHORT_PCM_SYNC
PCM_CLK
PCM_OUT
PCM_IN
1
2
3
4
5
6
7 8
1
2
3
4
5
6
7 8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8 Do Not Care
Do Not Care
Figure 9.13: Multi-slot Operation with 2 Slots and 8-bit Companded Samples
9.3.5
GCI Interface
CSR8640 BGA is compatible with the GCI, a standard synchronous 2B+D ISDN timing interface. The 2 64kbps B
channels are accessed when this mode is configured.
G-
T
W
-000
0222.2.3
PCM_SYNC
PCM_CLK
PCM_OUT
PCM_IN
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
Do Not
Care
Do Not
Care
B1 Channel
B2 Channel
Figure 9.14: GCI Interface
The start of frame is indicated by the rising edge of PCM_SYNC and runs at 8kHz.
9.3.6
Slots and Sample Formats
CSR8640 BGA receives and transmits on any selection of the first 4 slots following each sync pulse. Slot durations
are either 8 or 16 clock cycles:
■
8 clock cycles for 8-bit sample formats.
■
16 clock cycles for 8-bit, 13-bit or 16-bit sample formats.
CSR8640 BGA supports:
■
13-bit linear, 16-bit linear and 8-bit µ-law or A-law sample formats.
■
A sample rate of 8ksps.
■
Little or big endian bit order.
■
For 16-bit slots, the 3 or 8 unused bits in each slot are filled with sign extension, padded with zeros or a
programmable 3-bit audio attenuation compatible with some codecs.
Advance Information
This material is subject to CSR's non-disclosure agreement
© Cambridge Silicon Radio Limited 2011
Page 50 of 110
CS-209182-DSP1
CSR8640 BGA
Data Sheet
