5
Kalimba DSP
The Kalimba DSP is an open platform DSP enabling signal processing functions to be performed on over-air data
or codec data to enhance audio applications. Figure 5.1 shows the Kalimba DSP interfaces to other functional blocks
within CSR8640 BGA.
G-
T
W
-000
5522.2.2
Memory
Management
Unit
MCU Register Interface (including Debug)
DSP MMU Port
PIO In/Out
IRQ to Subsystem
IRQ from Subsystem
1
µs
Timer Clock
Programmable Clock = 80MHz
Data Memory
Inteface
Address
Generators
Instruction Decode
Program Flow
Clock Select
Internal Control Register
MMU Interface
Interrupt Controller
Timer
MCU Window
Flash Window
DEBUG
ALU
PIO
DS
P
P
ro
gr
a
m
Co
n
tr
ol
Re
gi
ste
rs
DSP RAMs
DM2
DM1
PM
Kalimba DSP Core
DSP, MCU and Memory Window Control
DSP Data Memory 2 Interface (DM2)
DSP Data Memory 1 Interface (DM1)
DSP Program Memory Interface (PM)
Figure 5.1: Kalimba DSP Interface to Internal Functions
The key features of the DSP include:
■
80MIPS performance, 24-bit fixed point DSP core
■
2 single‑cycle MACs; 24 x 24-bit multiply and 56-bit accumulate
■
32-bit instruction word
■
Separate program memory and dual data memory, allowing an ALU operation and up to 2 memory accesses
in a single cycle
■
Zero overhead looping, including a very low-power 32-instruction cache
■
Zero overhead circular buffer indexing
■
Single cycle barrel shifter with up to 56-bit input and 56-bit output
■
Multiple cycle divide (performed in the background)
■
Bit reversed addressing
■
Orthogonal instruction set
■
Low overhead interrupt
For more information see
Kalimba Architecture 3 DSP User Guide
.
Advance Information
This material is subject to CSR's non-disclosure agreement
© Cambridge Silicon Radio Limited 2011
Page 28 of 110
CS-209182-DSP1
CSR8640 BGA
Data Sheet
