Table 9.10 I²S Slave Mode Timing ..................................................................................................................... 58
Table 9.11 Digital Audio Interface Master Timing .............................................................................................. 59
Table 9.12 I²S Master Mode Timing Parameters, WS and SCK as Outputs ...................................................... 59
Table 10.1 Recommended Configurations for Power Control and Regulation ................................................... 60
Table 10.2 Pin States on Reset .......................................................................................................................... 67
Table 11.1 Battery Charger Operating Modes Determined by Battery Voltage and Current ............................. 69
Table 13.1 ESD Handling Ratings ...................................................................................................................... 87
Table 15.1 Chemical Limits for Green Semiconductor Products ........................................................................ 90
List of Equations
Equation 3.1 Crystal Calibration Using PSKEY_ANA_FTRIM_OFFSET .............................................................. 26
Equation 3.2 Example of PSKEY_ANA_FTRIM_OFFSET Value for 2402.0168MHz .......................................... 26
Equation 3.3 Example of PSKEY_ANA_FTRIM_OFFSET Value for 2401.9832MHz .......................................... 26
Equation 7.1 Baud Rate ....................................................................................................................................... 31
Equation 8.1 LED Current .................................................................................................................................... 35
Equation 8.2 LED PAD Voltage ............................................................................................................................ 35
Equation 9.1 IIR Filter Transfer Function, H(z) ..................................................................................................... 47
Equation 9.2 IIR Filter Plus DC Blocking Transfer Function, H
DC
(z) .................................................................... 47
Equation 9.3 PCM_CLK Frequency Generated Using the Internal 48MHz Clock ................................................ 56
Equation 9.4 PCM_SYNC Frequency Relative to PCM_CLK ............................................................................... 56
Advance Information
This material is subject to CSR's non-disclosure agreement
© Cambridge Silicon Radio Limited 2011
Page 12 of 110
CS-209182-DSP1
CSR8640 BGA
Data Sheet
