CSR BlueCore CSR8640 BGA, User Manual

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9.3.8 PCM Timing Information
Symbol Parameter Min Typ Max Unit
f
mclk
PCM_CLK frequency
4MHz DDS generation.
Selection of frequency
is programmable. See
Section 9.3.10.
-
128
- kHz 256
512
48MHz DDS
generation. Selection
of frequency is
programmable. See
Section 9.3.10.
2.9 - - kHz
- PCM_SYNC frequency for SCO connection - 8 - kHz
t
mclkh
(a)
PCM_CLK high 4MHz DDS generation 980 - - ns
t
mclkl
(a)
PCM_CLK low 4MHz DDS generation 730 - - ns
- PCM_CLK jitter
48MHz DDS
generation
- - 21 ns pk-pk
t
dmclksynch
Delay time from PCM_CLK high to PCM_SYNC
high
- - 20 ns
t
dmclkpout
Delay time from PCM_CLK high to valid
PCM_OUT
- - 20 ns
t
dmclklsyncl
Delay time from PCM_CLK low to PCM_SYNC
low (Long Frame Sync only)
- - 20 ns
t
dmclkhsyncl
Delay time from PCM_CLK high to PCM_SYNC
low
- - 20 ns
t
dmclklpoutz
Delay time from PCM_CLK low to PCM_OUT
high impedance
- - 20 ns
t
dmclkhpoutz
Delay time from PCM_CLK high to PCM_OUT
high impedance
- - 20 ns
t
supinclkl
Set-up time for PCM_IN valid to PCM_CLK low 20 - - ns
t
hpinclkl
Hold time for PCM_CLK low to PCM_IN invalid 0 - - ns
Table 9.6: PCM Master Timing
(a)
Assumes normal system clock operation. Figures vary during low-power modes, when system clock speeds are reduced.
Advance Information
This material is subject to CSR's non-disclosure agreement
© Cambridge Silicon Radio Limited 2011
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CSR8640 BGA
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