ConMed sabre 180, Service Manual

Page: 43 / 72

3-17
lines, WV0-WV7, determine which waveform is
selected by the microprocessor, and the lower
address lines, A0-A6, determine which byte of the
waveform is selected at a time. The lower address
counter (A3U15 and A3U16) cycles through its
count to sequentially select each byte of the wave-
form and to reload its own count modulus at the
beginning of each waveform. The selected byte of
the waveform is then parallel-loaded into shift
register A3U17, where it is serially-shifted out to
the buffers U13A and U13B one bit every 50
nanoseconds.
A3U14 is configured as a modulus 8 counter that
controls the parallel loading of the shift register
A3U17 and increments the lower waveform
address counter (A3U15 and A3U16). Both the
loading and incrementing occur on the rising
edge of the 20 MHz clock when /SRLOAD
(U14-11) goes low and then high. A3U14 also
generates 2.5 MHz and 10 MHz clocks from the
20 MHz oscillator Y1 for clocking the
Display/Keyboard Driver/Encoder A2U2 and the
microprocessor A3U3.
Each time /SRLOAD goes low and then high,
the lower waveform address counter formed by
A3U15 and A3U16 advances its count. The out-
puts from this counter (A0-A7) select the next 8-
bit word to be loaded into A3U17 from A3U18.
When the lower waveform address counter reach-
es it full count, i.e., the entire waveform has been
completely outputted, /CNTRLD goes low on
the next count and the address counter is pre-
loaded to the pattern presented to it by O0-O7 of
A3U18. This pattern sets the modulus of the
address counter and thus the length of the wave-
form bit pattern. /CTRLOAD also clears the shift
register A3U17 to zeros to prevent putting the
modulus pattern out to the power amplifier. Since
/CTRLOAD is low only at the beginning of a
waveform, it is an excellent point to use for a
scope trigger when examining waveforms (use
TP20).
U13 provides both buffer and enable functions
for the waveform generator. See Figure 3.5 for
representative gate waveforms.
3.4.8 Tone Generator
Refer to Figure 5.6b. The operation of the Tone
Generator is a voltage controlled current source
that is switched on and off at the frequency of the
desired tone. /TONE is generated by the micro-
processor A3U3 at the desired audio frequency
and is buffered by sections of A3U5 and A3U12
to generate the signal SPKR-. When SPKR- is
inactive, no current flows through speaker
A8SP1, thus there is no sound. When SPKR- is
low, the current flow through the speaker is deter-
mined by R16 (which sets the minimum sound
level per IEC 601-2-2 requirements) and the base
voltage of A3Q2.
A9R1 (the volume control pot) and A3R18 form
a voltage divider to set the base voltage of A3Q2.
The emitter voltage of A3Q2 is one diode drop
higher than its base voltage and is a constant for a
given base voltage. This controlled emitter volt-
age across R15 means a current is flowing
through A3Q2 that can be controlled by the base
voltage. That is how the volume is set for normal
operation. When an alarm is sounded, /LOUD
from the microprocessor (which is buffered by
sections of U5 and U12) forces the base voltage
of A3Q2 into saturation regardless of the setting
of the volume control pot. This is to assure that
an alarm cannot be turned down in volume.
3.5 CONTROLLER FIRMWARE
The behavior of the Controller is a function of
the custom program residing in the A3U1
EPROM memory. It must be replaced only with a
factory programmed part. Most failures of this
part may be traced to mishandling, particularly
due to static discharge or to a secondary failure
resulting from application of excessive voltage to
the circuit, as may occur if a voltage regulator
fails. However, since undetected EPROM failure
could escalate a minor failure to a serious conse-
quence in the O.R. environment, the program is
equipped with many fail detection and shutdown
features. Further, an independent external circuit
(the Watchdog Timer) guards against a malfunc-
tioning EPROM or 8031 operation. This safety
system is discussed in the following overview of
the firmware program.
3.5.1 RUN Mode
The following list of software functions begins
at Power On Reset or by a manual reset per-
formed by an internal CAL/RST/RUN switch.