ConMed sabre 180, Service Manual

Page: 39 / 72

3-13
combination of R6 and C6. In normal operation
WDT strobes will occur after stage 1 has timed
out (Q1=0) but before stage 2 times out
(Q2=1). The one-shot is retriggerable and the
rising edge of Q1 will restart the 15 msec timing
sequence in the second stage even though it may
not have completed its current time delay. Normal
operation is indicated by /WDTINT (Q2) never
going low.
The relay enable flag, RLYEN-Q from U10-10, is
reset on power-up. This permits the microproces-
sor (U3) to test the WDT during initialization
without allowing RF to appear at the outputs.
While RYLEN-Q is disabled (low), the WDT will
not lock up, permitting the software to test for
correct operation. This is done by strobing the
WDT early (less than 10 msec), late (greater than
15 msec) and looking for the generation of the
interrupt /WDTINT (Q2=0). The WDT is then
triggered within the correct time window (10 to
15 msec) and should result in /WDTINT remain-
ing high. If these results are obtained, the WDT
timer circuitry is operating normally.
After initialization is complete, the microproces-
sor generates a WDTSTB at the start of the first
normal program timing cycle. The relay enable
flag, RLYEN-Q, is set by the NOR gate, U10-5
and U10-6 both going low. After this, the pro-
gram enters the normal operation program loop.
If a WDTSTB is not generated within 15 msec of
the previous strobe, the second stage will time
out and Q2 will go low resulting in a /WDTINT.
Since RYLEN-Q and /Q2 (U7-9) are high, the
inputs to U6-4 and U6-5 are both true resulting
in its output (U6-6) going low. This resets the
first stage one shot. Now that Q1 (U7-6) cannot
go high, Q2 (U7-12) is prevented from being
retriggered. With the WDT Q2 output gone low,
the microprocessor will execute a WDT failure
interrupt routine in response to /WDTINT
falling, WDTFL will turn on the MACHINE
FAULT Lamp and /WDTFL will disable drive to
the power amplifier.
If the WDTSTB is generated before 10 msec,
while Q1 is high, the NAND gate (U6-1 and
U6-2) will both be high resulting in U6-3 going
low and resetting the second stage. This causes
the same results as the late strobe described
above.
Note that the signal which causes the WDT to
latch and ignore all subsequent WDTSTB pulses
is RYLEN-Q being high. The only way to reset
RYLEN-Q is a Power On Reset.
3.4.2 Power On Reset
The Power On Reset (POR) circuit consists
of a single chip specifically designed for this func-
tion, A3U4, and associated components R1, U5,
and Q3. The POR circuit mo5 Vdc (U4-
8) and the output signals RST (pin 5) and /RST
(pin 6) become active if +5 Vdc fails below 4.75
Vdc. The 8031 microprocessor operation is
specified down to 4.5 Vdc. This allows power
supply margin for proper power down of the con-
troller until reset occurs. When /RST is low, the
microprocessor is reset via the Inverter U5-12. At
the same time, the signal, RST, goes high which
is inverted by Q3 forcing a /RD. This prevents
inadvertent writes to the NOVRAM during
power transitions, when the control and
address/data busses are in unknown conditions.
On power up, RST and /RST are kept active for
a minimum of 250 msec to allow the power sup-
ply and microprocessor to stabilize.
The power monitor (U4), also provides an input
(pin 1) for direct connection to a switch (A3S1-
4). Any time /PB is low for over 10 msec, the
outputs RST and /RST become active. They
remain active for a minimum of 250 msec after
the switch is moved from the “/RST” position.
One last feature of this circuit is its function as a
secondary watchdog timer. This is enabled by the
connection of Address Latch Enable (ALE) from
the microprocessor (U3-30) to U4-7. The RST
and /RST outputs are forced to an active state
when the /ST input (U4-7) is not stimulated for
1.2 seconds. This function is not normally used
because it requires a failure in the microprocessor
and the Watchdog Timer circuitry. This is consid-
ered a double fault condition and the odds of the
two occurring simultaneously is very low. Also, it
is possible for ALE to continue in normal opera-
tion while other parts of the microprocessor are
not. The WDT circuit described previously is
used because it is not susceptible to this failure in
fault detection.