ConMed sabre 180, Service Manual

Page: 40 / 72

3-14
3.4.3 Digital I/O
The four digital ports of the 8031 (U3) are
functionally assigned as follows:
PORT 0 (P0.0 - P0.7). This port serves two digi-
tal functions: 8-bit data bus for communicating
with external I/O, and low-order address bus for
accessing external Program Memory.
PORT 1 (P1.0 - P1.7). This port is dedicated to
discrete inputs or outputs. Port 1.1 reads the
position of the default settings jumper, JMP1.
Port 1.2 generates the signal /RFEN used to con-
trol RF output. Port 1.3 is /LOUD which
bypasses the audio volume control during alarm
conditions. Port 1.4 reads the signal ARMCOMP
which is supplied from the comparator U23-13.
ARMCOMP is used during a software controlled
successive approximation routine to determine
contact resistance of the Return Electrode. Port
1.6 /NVEN (Non-volatile Enable), is a special
flag, which along with /CAL generated by A3S1,
allows the microprocessor to write to the Non-
volatile section of the NOVRAM (U2) during the
calibration routine. Port 1.7 handles serial data
and port P1.0 generates serial clock (SCLK) for
the last setting EEPROM (A2U4).
PORT 2 (P2.0 - P2.7). This port supplies the
high-order address bus which reads from external
Program Memory and writes to external I/O. All
I/O is memory mapped so that distinct addresses
access specific devices. The system is configured
so that only one device is addressed at a time.
PORT 3 (P3.0 - P3.7). This port generates
special signals used to control the overall system.
These are /RD, /WR for reading or writing to
external I/O, /PSEN (Program Store Enable)
which enables the external Program Memory to
the bus during instruction fetches, and ALE
(Address Latch Enable) used for latching the low-
order byte of address during access to external
Program Memory. Port 3.1 generates the signal,
/TONE, which is the source of the various audio
tones used to signal activation or alarm condi-
tions. Port 3.2 is the input for external interrupt,
/WDTINT, from the Watchdog Timer. Port 3.3
is the input for the external interrupt, /IFAIL,
generated by the current monitor.
The Address Decoder (U9), is used to select
external I/O devices for reading and writing.
High-order address to the decoder inputs (A10,
A11, and A12) cause the corresponding output
(Y0 -Y7) to go low. After address decode has sta-
bilized, either /RD or /WR will go low to execute
a data transfer with the addressed device.
Peripheral Interface Adapter (PIA), U11, is a
general purpose I/O device designed to expand
the number of addressable I/O lines available. It
has three additional 8-bit ports (PA - PC) or 24
individually programmable pins. Port A is config-
ured to read switch closures from hand and foot
controls; Port B supplies an address to the
Waveform Generator used to select specific out-
put waveforms depending on the mode and
power selections. Port C is used to activate the
required relays to direct RF output to the appro-
priate accessory, and to enable the RF power sup-
ply.
3.4.4 Memories
The program used by the microprocessor is stored
in external memory, the 32 K byte EPROM
(U1). It is programmed and verified at the facto-
ry to ensure correct operation of the ESU. The
memory is divided into 4 K byte pages. The odd
pages are used for run time code which is
accessed during normal operation of the electro-
surgical unit. The even pages can only be accessed
when switch, A3S1, is in the CAL position. This
gates the address line A12 through OR gate (U8-
3) to the EPROM. When A3S1 is in RUN, A12
is forced high.
Register U24 captures the low order address byte
(AD0 -AD7) when ALE goes True. The data is
then enabled on to the same bus when /PSEN
and ALE are both low (0,0). In this manner the
address/data bus (AD0 - AD7), alternates
between carrying the low order address for the
next instruction from the microprocessor and
reading the data, which is the code for the next
program step, back to the microprocessor. The
high order address bus (A8 - A12), is used for
addresses only and does not require latching since
the information is available during the entire
memory read operation. The only time /PSEN is
active is during a program instruction fetch.
When the microprocessor is addressing external