ConMed sabre 180, Service Manual

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3-15
I/O, such as the PIA or NOVRAM, /PSEN
remains high. AD0 - AD7 is an I/O bus whenev-
er /PSEN is high.
The Nonvolatile Random Access Memory
(NOVRAM), U2, is a 128 x 8 bit high speed sta-
tic RAM overlaid bit-for-bit with a non-volatile
electrically erasable PROM. This device stores the
calibration coefficients used by the microproces-
sor to control accurate power output levels and to
measure return electrode resistance. These values
are stored in the non-volatile portion of the
NOVRAM during the calibration procedure. In
order to change these numbers, switch A3S1
must be in the CAL position to allow the signals
/NVEN (Nonvolatile Enable) and /WR through
the OR gate (U8-8 and U8-11). During normal
operation, a write to the NOVRAM is not
allowed.
When the ESU is powered up, the data stored in
the non-volatile section of U2 is automatically
copied onto the static RAM where it is accessed
by the microprocessor via the address/data bus.
Each time the ESU is activated, the current set of
power, mode and pad selection settings are saved
in A2U4, an Electrically Erasable PROM
(EEPROM) which retains data without power.
The microcontroller communicates with A2U4
over a bidirectional, synchronous two-wire bus,
SDAT and SCLK. Write access requires a special
16 bit preamble, which provides good protection
against accidental alteration of stored data during
power transients. The contents are further pro-
tected by a stored 16 bit CRC code. If the micro-
controller detects a CRC error during a power-up
read, the settings will default to zero power, pure,
monopolar and dual.
3.4.5 Base Voltage Generator
The base voltage generator is schematically
depicted on the A3 Controller Board Schematic,
Figure 5.6b. It is microprocessor-controlled with
two analog feedback paths that can turn the base
voltage down in case of excessive power amplifier
current and high output voltage. The high voltage
shutback is not active in monopolar coag modes.
The base voltage generator is made up of an 8 bit
DAC (U20), a differential amplifier (1/4 of
U21), an inverting breakpoint summing amplifier
(1/4 of U21), and power transistor A8Q1. U20
provides the input voltage selected by the micro-
processor on the bus AD0 - AD7. R25 is a pas-
sive pull down required by the DAC to reach the
lower DAC output voltages. Since resistor R32
includes the power transistor A8Q1 in the opamp
feedback loop, the combination of Q1 and U21
(pins 1,2, and 3) may be considered as a power
opamp for analysis purposes.
The -ISENSE and IGND signals are developed in
the RF power amplifier on the Power Conversion
Board A4. These signals are generated by the
power amplifier supply current passing through
sense resistors A4R4 and R5. The resulting volt-
age is proportional to the total dc current used by
the RF power amplifier. The portion of U21 that
includes pin 5, 6, and 7 makes up a low pass fil-
tered differential voltage amplifier that amplifies
the -ISENSE voltage by 10. The resulting
ISENSE voltage is proportional 0.5 V/A to the
dc current drawn by RF power amplifier from the
RF supply. When ISENSE exceeds the voltage at
U21-3 by a diode voltage drop, the ISENSE
feedback loop becomes dominant and backs
VBASE down to maintain the RF power amplifi-
er current at its limit. This is independent of
microprocessor control and is an additional safety
feature.
During monopolar coag mode, either WV6,
WV7, or both will be high, thus forcing pin U8-
6 high, which in turn makes U12-12 go low. This
action prevents the VSENSE voltage from turn-
ing back VBASE to limit RF output voltage. In
all other modes, U12-12 floats and allows
VSENSE to be active. When VSENSE exceeds
the voltage at U21-3 by a diode voltage drop, the
VSENSE feedback loop becomes dominant and
turns VBASE down to limit the amount of RF
output voltage. This action occurs primarily at
high power settings of monopolar cut at high
load impedances to prevent unwanted arcing at
the active electrode.
The inverting breakpoint amplifier (pins 1,2, and
3 of U21) gain varies with the VDAC input volt-
age. Refer to Figure 3.6. When VDAC is in the
high range (producing a low VBASE since the
amplifier inverts), the incremental gain is
-R32/R26. This low gain provides a finer control