Programmable DC Power Supply 62000L Series User’s Manual
4-20
4.3.2.1 The Questionable Status Register
The Questionable Status register reports information about the power supply.
The bit 0 and bit 1 provides the information about the output CV/CC regulation. If the power
supply is/was in CC (constant current) mode, the bit 0 sets to 1. If the power supply is/was in
CV (constant voltage) mode, the bit 1 sets to 1.
The bit 8 ~ bit 10 provides information that one of the protection event is tripped. If the over
temperature protection (OTP) tripped event is detected, bit 8 sets to 1. If the over voltage
protection (OVP) tripped event is detected, bit 9 sets to 1. If the over current protection (OCP)
tripped event is detected, bit 10 sets to 1.
To read the Questionable Status register, use the command below.
STATus:QUEStionable?
.
Any or all of the Questionable Status Events can be reported in the Questionable Status
Summary bit (QUES, bit 3) of Status Byte register through the enable register. To set the
enable register mask, write a decimal value to the register using the following command.
STATus:QUEStionable:ENABle <value>
.
The bits of Questionable Status register are latched can only cleared by the command
STAT:QUES?
or
*CLS
.
Bit definition – Questionable status register
Bit
Decimal
value
Definition
0 Voltage
1
The power supply is/was in constant current
mode.
1 Current
2
The power supply is/was in constant voltage
mode.
2-7 Not used
0
Always set to 0.
8 OTP
256
The over temperature protection circuit has
tripped.
9 OVP
512
The over voltage protection circuit has tripped.
10 OCP
1024
The over current protection circuit has tripped.
11-15 Not used 0
Always set to 0.
4.3.2.2 The Standard Event Register
The Standard Event register reports the types of instrument events, such as power-on
detected, command syntax errors, command execution errors, self-test or calibration errors,
query errors, or when executing
*OPC
. All of these statuses can be reported in the Standard
Event summary bit 5 of the Status Byte register via the enable register. To set the enable
register mask, you have to use
*ESE
to write a decimal value to the register.
Note
An error status like Standard Event register bit 2, 3, 4, or 5 will record one or
more errors in the error queue. Use
SYST:ERR?
to read the error queue.
