Waiting for FPGA startup Flag
Available Processor Memory: 63MB
Waiting For MXD message
Ready to receive image on MXD
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Transferring control to the downloaded code.
MII:FCC1: Link is 100Mbps full duplex.
MII:FCC3: Timeout waiting for Autonegotiate done.
Obtaining IP and filename from BOOTP ..
HostIp is 10.7.20.124
This board's IP is 10.7.20.34
Boot file image is /
IP address of default gateway to other networks is 10.7.20.124
Subnet mask set to: 255.255.0.0
dcc3000_t1.elf, Release 4.1.0 [07/03/13 01:03:41 PM]
Copyright (C) 2013, Avaya Inc. All rights reserved
Initializing Buffer Mgmt
Available Processor Memory: 47MB
Initializing Utilities
Initializing Sys Init
Initializing STRM
Initializing CCB
RC=0
Initializing QMC
RC=0
Initializing SPAN
Initializing CAS
Initializing ISDN
HDLC Drive Init
hdlc_transmit_tsk(): Span Tx Started 9: status:0x0
MPS T1 ISDN USER SIDE
hdlc_transmit_tsk(): Span Rx Started 9: status:0x0
Initializing ECHO CANCELLER
Initializing Stream ENV
Stream Mgr: Accepting Connections Now on Stream Port. Law is being set to ulaw
===============
3. From the application processor, execute an srp -status command, and ensure all processes
are running.
vsh#mps.1,vos/MPSAP1-248-a {1} -> srp -status
NODE:PORT USER PID LINE STATE ENTERED STATE FLAGS
CMDLINE
MPSAP1-248-a:5999 root 18897 - RECOVERING Jul 11 08:31:34 C srp
Component: #common.0,gen/MPSAP1-248-a
MPSAP1-248-a:60964 root 18898 - RUNNING Jul 10 16:47:31 C
Testing the DCC and TPM Configuration
October 2014
Avaya Media Processing Server 500 Hardware Installation and Maintenance
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