Computer Telephony (CT) Bus
Voice and audio data is transmitted throughout the MPS 500 over a synchronized CT bus system.
Multiple physical and logical protocol layers are used to implement voice communications so that
conversations can be bridged on a non-blocking basis.
At the lowest level, the MPS 500 supports three PCM audio encoding formats: A-Law; Mu-Law; and
Adaptive Differential Pulse Coded Modulation (ADPCM). The PCM data is transmitted between
bridged lines using time division multiplexing (TDM). The TDM transmission layer enables bridging
of conversations within spans and across spans. For redundancy, multiple clocking sources provide
synchronization of the CT bus.
Note:
The TMS can also be populated with a Multiple DSP Module (MDM), in one or more of the
remaining open slots. Although the motherboard has local digital signal processors, the MDM
provides additional resources for systems that require them.
Multiple DSP Module (MDM)
The TMS motherboard contains six digital signal processors (DSP), which can be configured for
communications protocols and to provide resources. The MDM contains 12 DSPs for the
configuration of additional resources. There are no indicators or connectors on the front panel of the
MDM. The only visible indication that an MDM is installed in a TMS slot (instead of a blank in the
slot), is the presence of bend tabs near the center of the front bracket that secure it to the MDM
circuit board. The following diagram shows the front view of an MDM when mounted in slot 2 only.
Figure 5: MDM Front View
For information about configuration of resources and protocols, see
on
page 57.
Field Programmable Gate Arrays
The TMS and the modules that plug into it (that is, DCC and MDM) contain Field Programmable
Gate Arrays (FPGA). An FPGA is a generic microchip that has no inherent functionality. It contains
arrays of generic logic elements (for example, gates) that are software configurable. The software
that configures the FPGA is called an image, and the image typically commands the FPGA to
assume the functionality of a designed logic circuit. A hardware architecture based on FPGAs is
very powerful and flexible because:
• A greater degree of complex logic functionality can be achieved in a relatively
smaller board space with fewer circuit components, compared to where
MPS 500 System Hardware Overview
16
Avaya Media Processing Server 500 Hardware Installation and Maintenance
October 2014