67
32099DS–06/2010
AT32UC3L016/32/64
10.2.6
WDT
1.
Clearing the Watchdog Timer (WDT) counter in second half of timeout period will
issue a Watchdog reset
If the WDT counter is cleared in the second half of the timeout period, the WDT will immedi-
ately issue a Watchdog reset.
Fix/Workaround
Use twice as long timeout period as needed and clear the WDT counter within the first half
of the timeout period. If the WDT counter is cleared after the first half of the timeout period,
you will get a Watchdog reset immediately. If the WDT counter s not cleared at all, the time
before the reset will be twice as long as needed.
10.2.7
GPIO
1.
Clearing GPIO interrupt may fail
Writing a one to the GPIO.IFRC register to clear the interrupt will be ignored if interrupt is
enabled for the corresponding port.
Fix / Workaround
Disable the interrupt, clear the interrupt by writing a one to GPIO.IFRC, then enable the
interrupt.
10.2.8
SPI
1.
SPI disable does not work in SLAVE mode
SPI disable does not work in SLAVE mode.
Fix/Workaround
Read the last received data, then perform a software reset by writing a one to the Software
Reset bit in the Control Register (CR.SWRST).
2.
SPI Bad Serial Clock Generation on 2nd chip select when SCBR==1, CPOL==1, and
NCPHA==0
W h e n m u l t i p l e c h i p s e l e c t s a r e i n u s e , i f o n e o f t h e b a u d r a t e s i s e q u a l t o 1
(CSRn.SCBR==1) and one of the others is not equal to 1, and CSRn.CPOL==1 and
CSRn.NCPHA==0, an additional pulse will be generated on SCK.
Fix/Workaround
When multiple chip selects are in use, if one of the baudrates is equal to 1, the others must
also be equal to 1 if CSRn.CPOL==1 and CSRn.NCPHA==0.
3.
SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0
When CSR0.CSAAT==1 and mode fault detection is enabled (MR.MODFDIS==0), the SPI
module will not start a data transfer.
Fix/Workaround
Disable mode fault detection by writing a one to MR.MODFDIS.
4.
Disabling SPI has no effect on the SR.TDRE bit
Disabling SPI has no effect on SR.TDRE whereas the write data command is filtered when
SPI is disabled. This means that as soon as the SPI is disabled it becomes impossible to
reset the SR.TDRE bit by writing to TDR. So if the SPI is disabled during a PDCA transfer,
the PDCA will continue to write data to TDR (as SR.TDRE stays high) until its buffer is
empty, and all data written after the disable command is lost.
Fix/Workaround
Disable the PDCA, add 2 NOP (minimum), and disable the SPI. To continue the transfer,
enable the SPI and the PDCA.
