71
32099DS–06/2010
AT32UC3L016/32/64
10.4.3
HMATRIX
1.
In the PRAS and PRBS registers, the MxPR fields are only two bits
In the PRAS and PRBS registers MxPR fields are only two bits wide, instead of four bits.
The unused bits are undefined when reading the registers.
Fix/Workaround
Mask undefined bits when reading PRAS and PRBS.
10.4.4
SAU
1.
The SR.IDLE bit reads as zero
The IDLE bit in the Status Register (SR.IDLE) reads as zero.
Fix/Workaround
None.
2.
Open Mode is not functional
The Open Mode is not functional.
Fix/workaround
None.
3.
VERSION register reads 0x100
The VERSION register reads 0x100 instead of 0x110.
Fix/Workaround
None.
10.4.5
PDCA
1.
PCONTROL.CHxRES is nonfunctional
PCONTROL.CHxRES is nonfunctional. Counters are reset at power-on, and cannot be
reset by software.
Fix/Workaround
SW needs to keep history of performance counters.
2.
Transfer error will stall a transmit peripheral handshake interface
If a transfer error is encountered on a channel transmitting to a peripheral, the peripheral
handshake of the active channel will stall and the PDCA will not do any more transfers on
the affected peripheral handshake interface.
Fix/workaround
Disable and then enable the peripheral after the transfer error.
3.
VERSION register reads 0x120
The VERSION register reads 0x120 instead of 0x122.
Fix/Workaround
None.
10.4.6
Power Manager
1.
Clock sources will not be stopped in Static mode if the difference between CPU and
PBx division factor is larger than 4
If the division factor between the CPU/HSB and PBx frequencies is more than 4 when enter-
ing a sleep mode where the system RC oscillator (RCSYS) is turned off, the high speed
clock sources will not be turned off. This will result in a significantly higher power consump-
tion during the sleep mode.
Fix/Workaround
