64
32099DS–06/2010
AT32UC3L016/32/64
10.1.10
PWMA
1.
BUSY bit is never cleared after writes to the Control Register (CR)
When writing a non-zero value to CR.TOP, CR.SPREAD, or CR.TCLR when the PWMA is
disabled (CR.EN==0), the BUSY bit in the Status Register (SR.BUSY) will be set, but never
cleared.
Fix/Workaround
When writing a non-zero value to CR.TOP, CR.SPREAD, or CR.TCLR, make sure the
PWMA is enabled, or simultaneously enable the PWMA by writing a one to CR.EN.
2.
Incoming peripheral events are discarded during duty cycle register update
Incoming peripheral events to all applied channels will be discarded if a duty cycle update is
received from the user interface in the same PWMA clock period.
Fix/Workaround
Ensure that duty cycle writes from the user interface are not performed in a PWMA clock
period when an incoming peripheral event is expected.
10.1.11
CAT
1.
CAT asynchronous wake will be delayed by one AST peripheral event period
If the CAT detects a condition that should asynchronously wake the chip in Static mode, the
asynchronous wake will not occur until the next AST event. For example, if the AST is gen-
erating peripheral events to the CAT every 50 milliseconds, and the CAT detects a touch at
t=9200 milliseconds, the asynchronous wake will occur at t=9250 milliseconds.
Fix/Workaround
None.
10.1.12
aWire
1.
aWire CPU clock speed robustness
The aWire memory speed request command counter wraps at clock speeds below approxi-
mately 5kHz.
Fix/Workaround
None.
2.
The aWire debug interface is reset after leaving Shutdown mode
If the aWire debug mode is used as debug interface and the program enters Shutdown
mode, the aWire interface will be reset when the device receives a wake-up either from the
WAKE_N pin or the AST.
Fix/Workaround
None.
10.1.13
I/O Pins
1.
PA17 has low ESD tolerance
PA17 only tolerates 500V ESD pulses (Human Body Model).
Fix/Workaround
Care must be taken during manufacturing and PCB design.
