Atmel AT32UC3L016 Manual Download Page 57

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32099DS–06/2010

AT32UC3L016/32/64

Figure 8-2.

QFN-48 Package Drawing

Note:

The exposed pad is not connected to anything.

Table 8-5.

Device and Package Maximum Weight

140

Table 8-6.

Package Characteristics

Moisture Sensitivity Level

MSL3

Table 8-7.

Package Reference

JEDEC Drawing Reference

M0-220

JESD97 Classification

Summary of Contents for AT32UC3L016

Page 1: ...8Kbytes 16Kbytes Flash Interrupt Controller INTC Autovectored Low Latency Interrupt Service with Programmable Priority External Interrupt Controller EIC Peripheral Event System for Direct Peripheral...

Page 2: ...ors QTouch Library Support Capacitive Touch Buttons Sliders and Wheels QTouch and QMatrix Acquisition On Chip Non Intrusive Debug System Nexus Class 2 Runtime Control Non Intrusive Data and Program Tr...

Page 3: ...raries to be programmed into the device The secure libraries can be executed while the CPU is in Secure State but not read by non secure software in the device The device can thus be shipped to end co...

Page 4: ...ined reference window The Capacitive Touch CAT module senses touch on external capacitive touch sensors using the QTouch technology Capacitive touch sensors use no external mechanical components unlik...

Page 5: ...ERS BUS 64 32 16 KB FLASH S FLASH CONTROLLER EVTO_N AVR32UC CPU NEXUS CLASS 2 OCD INSTR INTERFACE DATA INTERFACE MEMORY INTERFACE LOCAL BUS 16 8 KB SRAM MEMORY PROTECTION UNIT LOCAL BUS INTERFACE FREQ...

Page 6: ...us Timers 1 Timer Counter Channels 6 PWM channels 36 Frequency Meter 1 Watchdog Timer 1 Power Manager 1 Secure Access Unit 1 Glue Logic Controller 1 Oscillators Digital Frequency Locked Loop 40 150 MH...

Page 7: ...GND 1 PA09 2 PA08 3 PA03 4 PB12 5 PB00 6 PB02 7 PB03 8 PA22 9 PA06 10 PA00 11 PA05 12 PA02 13 PA01 14 PA07 15 PB01 16 VDDIN 17 VDDCORE 18 GND 19 PB05 20 PB04 21 RESET_N 22 PB10 23 PA21 24 PA14 36 VDDA...

Page 8: ...PA06 10 PA00 11 PA05 12 PA02 13 PA01 14 PA07 15 PB01 16 VDDIN 17 VDDCORE 18 GND 19 PB05 20 PB04 21 RESET_N 22 PB10 23 PA21 24 PA14 36 VDDANA 35 ADVREFP 34 GNDANA 33 PB08 32 PB07 31 PB06 30 PB09 29 PA0...

Page 9: ...B 7 10 PA06 6 VDDIO High drive I O 5V tolerant SPI SCK USART2 TXD USART1 CLK TC0 B0 PWMA PWMA 6 SCIF GCLK 1 CAT CSB 1 15 PA07 7 VDDIO TWI Normal I O SPI NPCS 0 USART2 RXD TWIMS1 TWALM TWIMS0 TWCK PWMA...

Page 10: ...DIO Normal I O USART3 RTS USART3 CLK SPI MISO TC0 A2 PWMA PWMA 25 ACIFB ACAN 2 SCIF GCLK 1 CAT CSB 11 8 PB03 35 VDDIO Normal I O USART3 CTS USART3 CLK SPI MOSI TC0 B2 PWMA PWMA 26 ACIFB ACBP 2 TC1 A2...

Page 11: ...er a number of pins irre spectively of the I O Controller configuration Two different OCD trace pin mappings are possible depending on the configuration of the OCD AXS register For details see the AVR...

Page 12: ...AOUT pin will only be actice after the aWire is enabled and the 2_PIN_MODE command has been sent The WAKE_N pin is always enabled Please refer to Section 6 1 4 on page 40 for constraints on the WAKE_N...

Page 13: ...Analog Signal Analog ADP1 ADP0 Drive Pin for resistive touch screen Output PRND Pseudorandom output signal Output TRIGGER External trigger Input aWire AW DATA aWire data I O DATAOUT aWire data output...

Page 14: ...2 Output primary location Analog XOUT32_2 Crystal 32 Output secondary location Analog Serial Peripheral Interface SPI MISO Master In Slave Out I O MOSI Master Out Slave In I O NPCS3 NPCS0 SPI Peripher...

Page 15: ...y Power Input 1 62V to 3 6V VDDIO should always be equal to or lower than VDDIN VDDANA Analog Power Supply Power Input 1 62V to 1 98V ADVREFP Analog Reference Voltage Power Input TBD to 1 98V VDDIN Vo...

Page 16: ...ins have the characteristics indicated in the Electrical Characteristics section Selected pins are also SMBus compliant refer to Section 3 2 on page 9 As required by the SMBus specification these pins...

Page 17: ...gnal will be defined by VDDIN 3 4 8 2 XOUT32_2 function PA20 selects RC32OUT as default enabled after reset This function is not automatically dis abled when the user enables the XOUT32_2 function on...

Page 18: ...ed to allow a variety of microarchitectures enabling the AVR32 to be implemented as low mid or high performance processors AVR32 extends the AVR family into the world of 32 and 64 bit applications Thr...

Page 19: ...ta RAMs internal to the CPU allows fast access to the RAMs reduces latency and guarantees deterministic timing Also power consumption is reduced by not needing a full High Speed Bus access for memory...

Page 20: ...complete and in this case the instruction resides in the ID and EX stages for the required num ber of clock cycles Since there is only three pipeline stages no internal data forwarding is required an...

Page 21: ...dler can therefore use R8 R12 freely Upon interrupt completion the old R8 R12 registers and status register are restored and execution continues at the return address stored popped from stack The stac...

Page 22: ...ctions All coprocessor instructions if no coprocessors are present retj incjosp popjc pushjc tlbr tlbs tlbw cache 4 3 2 6 CPU and Architecture Revision Three major revisions of the AVR32UC CPU current...

Page 23: ...C FINTPC INT1PC SMPC R7 R5 R6 R4 R11 R9 R10 R8 R3 R1 R2 R0 SP_SYS LR Bit 0 Bit 31 PC SR R12 INT0PC FINTPC INT1PC SMPC R7 R5 R6 R4 R11 R9 R10 R8 R3 R1 R2 R0 SP_SYS LR Bit 0 Bit 31 PC SR R12 INT0PC FINT...

Page 24: ...R32 can be set in a debug state which allows implementation of software monitor rou tines that can read out and alter system information for use during application development This implies that all sy...

Page 25: ...ing correct sequencing of any instructions following a mtsr instruction For detail on the system registers refer to the AVR32UC Technical Reference Manual Table 4 3 System Registers Reg Address Name F...

Page 26: ...32UC 71 284 TLBEAR Unused in AVR32UC 72 288 MMUCR Unused in AVR32UC 73 292 TLBARLO Unused in AVR32UC 74 296 TLBARHI Unused in AVR32UC 75 300 PCCNT Unused in AVR32UC 76 304 PCNT0 Unused in AVR32UC 77 3...

Page 27: ...R addresses This allows the interrupt controller to directly specify the ISR address as an address 90 360 MPUPSR2 MPU Privilege Select Register region 2 91 364 MPUPSR3 MPU Privilege Select Register re...

Page 28: ...mask bits corresponding to all sources with equal or lower priority This inhibits acceptance of other events of the same or lower priority except for the critical events listed above Software may choo...

Page 29: ...r Events Several different event handler entry points exist In AVR32UC the reset address is 0x80000000 This places the reset address in the boot flash memory area TLB miss exceptions and scall have a...

Page 30: ...on B is younger than an instruction A if it was sent down the pipeline later than A The addresses and priority of simultaneous events are shown in Table 4 4 on page 31 Some of the exceptions are unuse...

Page 31: ...equest External input First non completed instruction 12 EVBA 0x14 Instruction Address CPU PC of offending instruction 13 EVBA 0x50 ITLB Miss MPU PC of offending instruction 14 EVBA 0x18 ITLB Protecti...

Page 32: ...l High Speed SRAM Single cycle access at full speed 16Kbytes AT32UC3L064 AT32UC3L032 8Kbytes AT32UC3L016 5 2 Physical Memory Map The system bus is implemented as a bus matrix All system bus addresses...

Page 33: ...ST Asynchronous Timer AST 0xFFFF2000 WDT Watchdog Timer WDT 0xFFFF2400 EIC External Interrupt Controller EIC 0xFFFF2800 FREQM Frequency Meter FREQM 0xFFFF2C00 GPIO General Purpose Input Output Control...

Page 34: ...s bus Also since the local bus runs at CPU speed one write or read operation can be performed per clock cycle to the local bus mapped GPIO registers 0xFFFF4800 TWIM1 Two wire Master Interface TWIM1 0x...

Page 35: ...ite only Output Value Register OVR WRITE 0x40000050 Write only SET 0x40000054 Write only CLEAR 0x40000058 Write only TOGGLE 0x4000005C Write only Pin Value Register PVR 0x40000060 Read only 1 Output D...

Page 36: ...nominal to 1 8V with a load of up to 60 mA The regulator supplies the output voltage on VDDCORE The regulator may only be used to drive internal circuitry in the device VDDCORE should be externally c...

Page 37: ...nd its output feeds VDDCORE Figure 6 2 shows the power schematics to be used for 3 3V sin gle supply mode All I O lines will be powered by the same power VDDIN VDDIO Figure 6 2 3 3V Single Power Suppl...

Page 38: ...IO and VDDCORE are powered by a single 1 8V supply as shown in Figure 6 3 All I O lines will be powered by the same power VDDIN VDDIO VDDCORE Figure 6 3 1 8V Single Power Supply Mode VDDIO VDDCORE Lin...

Page 39: ...on page 9 for description of power supply for each I O line Refer to the Power Manager chapter for a description of what parts of the system are powered in Shutdown mode Important note As the regulato...

Page 40: ...a reset state by the Power On Reset circuitry for a short time to allow the power to stabilize throughout the device After reset the device will use the System RC Oscillator RCSYS as clock source Ple...

Page 41: ...rating only and functional opera tion of the device at these or other condi tions beyond those indicated in the operational sections of this specification is not implied Exposure to absolute maxi mum...

Page 42: ...VVDDIN VVDDCORE 1 8V TA 25 C Oscillators Table 7 3 Supply Rise Rates and Order Symbol Parameter Rise Rate Min Max Unit Comment VVDDIO DC supply peripheral I Os 0 2 5 V s VVDDIN DC supply peripheral I...

Page 43: ...re inactive with internal pull up Flash enabled in high speed mode POR33 disabled Table 7 5 Power Consumption for Different Modes Mode Conditions Measured on Consumption Typ Unit Active CPU running a...

Page 44: ...istics Amp0 VDDIN VDDCORE VDDANA VDDIO Amp0 VDDIN VDDCORE VDDANA VDDIO Table 7 6 Normal I O Pad Characteristics 1 Symbol Parameter Condition Min Typ Max Units RPULLUP Pull up resistance 75 100 145 kOh...

Page 45: ...yp Max Units RPULLUP Pull up resistance PA06 30 50 110 kOhm PA02 PB01 RESET 75 100 145 PA08 PA09 10 20 45 VIL Input low level voltage VVDD 3 0V 0 3 0 3 VVDD V VVDD 1 62V 0 3 0 3 VVDD VIH Input high le...

Page 46: ...ut high level voltage VVDD 3 6V 0 7 VVDD 5 5 V VVDD 1 98V 0 7 VVDD 5 5 VOL Output low level voltage VVDD 3 0V IOL 6mA 0 4 V VVDD 1 62 V IOL 4mA 0 4 VOH Output high level voltage VVDD 3 0V IOH 6mA VVDD...

Page 47: ...tor OSC32K Characteristics Figure 7 3 and the equation above also applies to the 32KHz oscillator connection The user must choose a crystal oscillator where the crystal load capacitance CL is within t...

Page 48: ...p Max Unit fOUT Output frequency 40 150 MHz fREF Reference frequency 8 150 kHz FINE resolution FINE 100 all COARSE values 0 25 Accuracy Fine lock fREF 32kHz SSG disabled 0 1 0 5 Accurate lock fREF 32k...

Page 49: ...RE 1 8V 88 120 152 MHz Temperature drift 5 Duty Duty cycle 40 50 60 Table 7 16 32kHz RC Oscillator Characteristics Symbol Parameter Conditions Min Typ Max Unit fOUT Output frequency T 25 C VVDDIO 3 3V...

Page 50: ...tics Symbol Parameter Condition Min Typ Max Units VVDDIN Input voltage range 1 98 3 3 3 6 V VVDDCORE Output voltage VVDDIN 1 98V 1 8 V Output voltage accuracy IOUT 0 1mA to 60mA VVDDIN 2 2V 2 IOUT 0 1...

Page 51: ...source 460 Table 7 24 External Voltage Reference Input Symbol Parameter Conditions Min Typ Max Units VADVREFP Reference voltage range VADVREFP VVDDANA 1 62 1 98 V Current consumption on VVDDANA On 13...

Page 52: ...fset error 1 Gain error 1 Table 7 27 Transfer Characteristics 8 bit Resolution Mode Parameter Conditions Min Typ Max Units Table 7 28 Analog Comparator Characteristics Symbol Parameter Condition Min T...

Page 53: ...7 4 POR18 Operating Principles Table 7 29 Power on Reset Characteristics Symbol Parameter Condition Min Typ Max Units VPOT Voltage threshold on VVDDCORE rising T 25 C 1 45 V VPOT Voltage threshold on...

Page 54: ...cs Symbol Parameter Condition Min Typ Max Units VPOT Voltage threshold on VVDDIN rising T 25 C 1 49 V VPOT Voltage threshold on VVDDIN falling 1 45 Reset V VDDIN VPOT VPOT Table 7 31 Temperature Senso...

Page 55: ...ided in the Section 7 5 on page 42 TA ambient temperature C From the first equation the user can derive the estimated lifetime of the chip and decide if a cooling device is necessary or not If a cooli...

Page 56: ...e Drawings Figure 8 1 TQFP 48 Package Drawing Table 8 2 Device and Package Maximum Weight 140 mg Table 8 3 Package Characteristics Moisture Sensitivity Level MSL3 Table 8 4 Package Reference JEDEC Dra...

Page 57: ...e Drawing Note The exposed pad is not connected to anything Table 8 5 Device and Package Maximum Weight 140 mg Table 8 6 Package Characteristics Moisture Sensitivity Level MSL3 Table 8 7 Package Refer...

Page 58: ...igure 8 3 TLLGA 48 Package Drawing Table 8 8 Device and Package Maximum Weight 39 3 mg Table 8 9 Package Characteristics Moisture Sensitivity Level MSL3 Table 8 10 Package Reference JEDEC Drawing Refe...

Page 59: ...s is allowed per component Table 8 11 Soldering Profile Profile Feature Green Package Average Ramp up Rate 217 C to Peak 3 C s max Preheat Temperature 175 C 25 C 150 200 C Time Maintained Above 217 C...

Page 60: ...Tape Reel AT32UC3L064 D3HES ES TLLGA 48 JESD97 Classification E4 AT32UC3L064 D3HT Tray AT32UC3L064 D3HR Tape Reel AT32UC3L032 AT32UC3L032 AUT Tray TQFP 48 JESD97 Classification E3 AT32UC3L032 AUR Tap...

Page 61: ...the flash controller in zero wait state mode FCR FWS 0 Solution 2 Configure the HMATRIX master 1 CPU Instruction to use the unlimited burst length transfer mode MCFG1 ULBT 0 and the HMATRIX slave 0 F...

Page 62: ...released one AST clock cycle after the BUSY bit in the Status Register SR BUSY is cleared If entering sleep mode directly after the BUSY bit is cleared the part will wake up immediately Fix Workaround...

Page 63: ...possible to reset the SR TDRE bit by writing to TDR So if the SPI is disabled during a PDCA transfer the PDCA will continue to write data to TDR as SR TDRE stays high until its buffer is empty and all...

Page 64: ...T 1 CAT asynchronous wake will be delayed by one AST peripheral event period If the CAT detects a condition that should asynchronously wake the chip in Static mode the asynchronous wake will not occur...

Page 65: ...the HMATRIX master 1 CPU Instruction to use the unlimited burst length transfer mode MCFG1 ULBT 0 and the HMATRIX slave 0 FLASHCDW to use the maximum slot cycle limit SCFG0 SLOT_CYCLE 255 10 2 3 Powe...

Page 66: ...back to original main clock source Solution 2 Only turn off the CFD while running the main clock on RCSYS 10 2 4 SCIF 1 PCLKSR OSC32RDY bit might not be cleared after disabling OSC32K In some cases t...

Page 67: ...n the Control Register CR SWRST 2 SPI Bad Serial Clock Generation on 2nd chip select when SCBR 1 CPOL 1 and NCPHA 0 When multiple chip selects are in use if one of the baudrates is equal to 1 CSRn SCB...

Page 68: ...n writing a non zero value to CR TOP CR SPREAD or CR TCLR when the PWMA is disabled CR EN 0 the BUSY bit in the Status Register SR BUSY will be set but never cleared Fix Workaround When writing a non...

Page 69: ...on 2 Pull down or up XIN0 and XOUT0 with 1Mohm resistor 2 In 3 3V Single Supply Mode the Analog Comparator inputs affects the device s ability to start When using the 3 3V Single Supply Mode the state...

Page 70: ...is 1 Fix Workaround Solution 1 Configure the flash controller in zero wait state mode FCR FWS 0 Solution 2 Configure the HMATRIX master 1 CPU Instruction to use the unlimited burst length transfer mod...

Page 71: ...round SW needs to keep history of performance counters 2 Transfer error will stall a transmit peripheral handshake interface If a transfer error is encountered on a channel transmitting to a periphera...

Page 72: ...FIG register reads 0x4F The CONFIG register reads 0x4F instead of 0x43 Fix Workaround None 4 PB writes via debugger in sleep modes are blocked during sleepwalking During sleepwalking PB writes perform...

Page 73: ...interrupts BODDET SM33DET and VREGOK interrupts will not be gen erated if they occur when writing to ICR 3 FINE value for DFLL is not correct when dithering is disabled In open loop mode the FINE val...

Page 74: ...lock too early The DFLLIF might indicate coarse lock too early the DFLL will lose coarse lock and regain it later Fix Workaround Use max step size DFLL0MAXSTEP MAXSTEP of 4 or higher 11 DFLLIF dither...

Page 75: ...e if the OSC32K clock is ready The OSC32K clock is ready when the FREQM measures a non zero frequency 10 4 8 AST 1 AST wake signal is released one AST clock cycle after the BUSY bit is cleared After w...

Page 76: ...interrupt is enabled for the pin Fix Workaround Enable interrupt for the corresponding pin then clear the interrupt 2 VERSION register reads 0x210 The VERSION register reads 0x210 instead of 0x211 Fix...

Page 77: ...s that as soon as the SPI is disabled it becomes impossible to reset the SR TDRE bit by writing to TDR So if the SPI is disabled during a PDCA transfer the PDCA will continue to write data to TDR as S...

Page 78: ...an cause a problem if software waits for SR IDLE to go high and then immediately disables the TWIM by writing a one to CR MDIS Disabling the TWIM causes the TWCK and TWD pins to go high immediately so...

Page 79: ...AD or CR TCLR make sure the PWMA is enabled or simultaneously enable the PWMA by writing a one to CR EN 6 Incoming peripheral events are discarded during duty cycle register update Incoming peripheral...

Page 80: ...ead of three bits wide Only values 0 1 and 2 can be written to this register CONFW WEVEN is in bit position 10 instead of 11 Fix Workaround Only write values 0 1 and 2 to CONFW WEVSRC When reading CON...

Page 81: ...next AST event For example if the AST is gen erating peripheral events to the CAT every 50 milliseconds and the CAT detects a touch at t 9200 milliseconds the asynchronous wake will occur at t 9250 m...

Page 82: ...when the voltage on analog inputs is close to VDDIO 2 Fix Workaround None 3 PA02 PB01 PB04 PB05 and RESET_N have half of the pull up strength Pins PA02 PB01 PB04 PB05 and RESET_N have half of the spe...

Page 83: ...O in sleep modes If the OSC0 is enabled in crystal mode when entering a sleep mode where the OSC0 is dis abled this will lead to an increased power consumption in VDDIO Fix Workaround Solution 1 Disab...

Page 84: ...es Considerations Added Following pins have high drive capability PA02 PA06 PA08 PA09 and PB01 Some TWI0 pins are SMBUS compliant PA21 PB04 PB05 4 HMATRIX Masters PDCA is master 4 not master 3 SAU is...

Page 85: ...ignal names 20 ACIFB CONFW WEVSRC is bit 8 10 CONFW EWEVEN is bit 11 CONF EVENP and CONF EVENN bits are swapped 21 CAT Matrix size is 16 by 8 not 18 by 8 22 Electrical Characteristics General update 2...

Page 86: ...ture 18 4 3 The AVR32UC CPU 19 4 4 Programming Model 23 4 5 Exceptions and Interrupts 27 5 Memories 32 5 1 Embedded Memories 32 5 2 Physical Memory Map 32 5 3 Peripheral Address Map 33 5 4 CPU Local B...

Page 87: ...al Characteristics 55 8 1 Thermal Considerations 55 8 2 Package Drawings 56 8 3 Soldering Profile 59 9 Ordering Information 60 10 Errata 61 10 1 Rev E 61 10 2 Rev D 65 10 3 Rev C 69 10 4 Rev B 69 11 D...

Page 88: ...ght is granted by this document or in connection with the sale of Atmel products EXCEPT AS SET FORTH IN ATMEL S TERMS AND CONDI TIONS OF SALE LOCATED ON ATMEL S WEB SITE ATMEL ASSUMES NO LIABILITY WHA...

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