73
32099DS–06/2010
AT32UC3L016/32/64
If all the following operating conditions are true, exiting sleep walking might lead to
instability:
- T he O S C 0 i s e n ab l e d i n e x t er n al c l o c k m o de ( O S C C T R L 0 .O S C E N = = 1 a n d
OSCCTRL0.MODE == 0)
-A sleep mode where the OSC0 is automatically disabled is entered
-The chip enters sleep walking
Fix/Workaround
Do not run OSC0 in external clock mode if sleep walking is expected to be used.
10.4.7
SCIF
1.
The DFLL should be slowed down before disabled
The frequency of the DFLL should be set to minimum before disabled.
Fix/Workaround
Before disabling the DFLL the value of the COARSE register should be set to zero.
2.
Writing to ICR masks new interrupts received in the same clock cycle
Writing to ICR masks any new SCIF interrupt received in the same clock cycle, regardless of
write value.
Fix/Workaround
For every interrupt except BODDET, SM33DET, and VREGOK the CLKSR register can be
read to detect new interrupts. BODDET, SM33DET, and VREGOK interrupts will not be gen-
erated if they occur when writing to ICR.
3.
FINE value for DFLL is not correct when dithering is disabled
In open loop mode, the FINE value used by the DFLL DAC is offset by two compared to the
value written to the DFLL0CONF.FINE field. I.e. the value to the DFLL DAC is
DFLL0CONF.FINE-0x002. If DFLL0CONF.FINE is written to 0x000, 0x001, or 0x002 the
value to the DFLL DAC will be 0x1FE, 0x1FF, or 0x000 respectively.
Fix/Workaround
Write the desired value added by two to the DFLL0CONF.FINE field.
4.
BODVERSION register reads 0x100
The BODVERSION register reads 0x100 instead of 0x101.
Fix/Workaround
None.
5.
BRIFA is non-functional
BRIFA is non-functional.
Fix/Workaround
None.
6.
VREGCR.DEEPMODEDISABLE bit is not readable
VREGCR.DEEPMODEDISABLE bit is not readable.
Fix/Workaround
None.
7.
DFLL step size should be 7 or lower below 30 MHz
If max step size is above 7, the DFLL might not lock at the correct frequency if the target fre-
quency is below 30 MHz.
Fix/Workaround
If the target frequency is below 30 MHz, use max step size (DFLL0MAXSTEP.MAXSTEP) of
7 or lower.
