20
32099DS–06/2010
AT32UC3L016/32/64
Figure 4-1.
Overview of the AVR32UC CPU
4.3.1
Pipeline Overview
AVR32UC has three pipeline stages, Instruction Fetch (IF), Instruction Decode (ID), and Instruc-
tion Execute (EX). The EX stage is split into three parallel subsections, one arithmetic/logic
(ALU) section, one multiply (MUL) section, and one load/store (LS) section.
Instructions are issued and complete in order. Certain operations require several clock cycles to
complete, and in this case, the instruction resides in the ID and EX stages for the required num-
ber of clock cycles. Since there is only three pipeline stages, no internal data forwarding is
required, and no data dependencies can arise in the pipeline.
shows an overview of the AVR32UC pipeline stages.
AVR32UC CPU pipeline
Instruction memory controller
High
Speed
Bus
master
MPU
Hi
g
h Spee
d Bus
Hi
g
h Spee
d Bus
OCD
system
OC
D i
n
te
rf
ac
e
In
te
rr
up
t co
nt
ro
ller
in
te
rfa
ce
High
Speed
Bus slave
Hi
g
h Spee
d Bus
High Speed Bus master
Power/
Reset
control
Res
et in
te
rfa
ce
CPU Local
Bus
master
CPU Loc
a
l Bus
Data memory controller
CPU RAM
