15
32099DS–06/2010
AT32UC3L016/32/64
Note:
1. ADCIFB: AD3 does not exist.
CLK
Clock
I/O
CTS
Clear To Send
Input
Low
RTS
Request To Send
Output
Low
RXD
Receive Data
Input
TXD
Transmit Data
Output
Table 3-7.
Signal Descriptions List
Table 3-8.
Signal Description List, continued
Signal Name
Function
Type
Active
Level
Comments
Power
VDDCORE
Core Power Supply / Voltage Regulator Output
Power
Input/Output
1.62V to 1.98V
VDDIO
I/O Power Supply
Power Input
1.62V to 3.6V. VDDIO should
always be equal to or lower than
VDDIN.
VDDANA
Analog Power Supply
Power Input
1.62V to 1.98V
ADVREFP
Analog Reference Voltage
Power Input
TBD to 1.98V
VDDIN
Voltage Regulator Input
Power Input
1.62V to 3.6V
(1)
GNDANA
Analog Ground
Ground
GND
Ground
Ground
Auxiliary Port - AUX
MCKO
Trace Data Output Clock
Output
MDO5 - MDO0
Trace Data Output
Output
MSEO1 - MSEO0
Trace Frame Control
Output
EVTI_N
Event In
Input
Low
EVTO_N
Event Out
Output
Low
General Purpose I/O pin
PA22 - PA00
Parallel I/O Controller I/O Port 0
I/O
PB12 - PB00
Parallel I/O Controller I/O Port 1
I/O
1.