Model 8640B
TM 9-4935-601-14-7&P
SERVICE SHEET 4
PRINCIPLES OF OPERATION
Internal Count Mode
When the internal count mode is selected, the 256 512 MHz signal from the Frequency Counter Buffer Amplifier (Service Sheet 2)
is first divided by 64 and then is counted by the Up/Down Counter (used in the count-up mode). An ECL to TTL Translator shifts
the logic levels of the +64 Divider to be compatible with the counter.
The counter's time base is derived from a 5 MHz Reference Oscillator (or an external reference) and is divided by a divide-by-N
counter (the Time Base Decoder). The division ratio is programmed by the frequency RANGE and EXPAND X10 and X100
switches. The Up/Down Counter drives the Storage Buffers which store the previous count while the counter is counting. The
Counter Display is driven from the Storage Buffers. The Decimal Point Decoder decodes the decimal point information on the
RANGE switch and the EXPAND switches and drives the display's decimal points. The Overflow Detector senses when the count
overflows the number of digits available on the display and turns on the OVERFLOW annunciator.
External Count Mode
When the external count mode is selected, the external signal enters the counter input in place of the RF oscillator's output.
When the 0 10 MHz mode is selected, the 64 Divider is bypassed. The EXT 0 550 MHz and 0 10 MHz switches also program
the Time Base Decoder; otherwise, the counter's operation is identical to the internal count mode.
Phase Lock Mode
When the LOCK switch is first depressed, the counter continues to count up until the present count is terminated. The count is
then stored in the Storage Buffers, and the counter enters the phase lock mode. The count now proceeds with the count from the
Storage Buffers being preset into the Up/Down Counter. The counter counts down to zero and then underflows (i.e., all counters
at the state of nine) and the time of occurrence of the underflow is compared with the termination of the time base cycle in the Null
Phase Detector (at the underflow the counter is once again preset from the buffers and continues counting toward zero). The error
from the detector adjusts the tuning of the RF Oscillator (Service Sheet 2) to bring the average error to zero. When the Error
Detector senses the tuning voltage nearing its limit, phase lock is broken, the counter reverts to the normal count-up mode, and
the Flash Oscillator is enabled which blinks the display.
TROUBLESHOOTING
It is assumed that a problem has been isolated to the counter/lock circuits as a result of using the overall block diagram.
Troubleshoot by using the test equipment and procedures specified below.
Test Equipment
Digital Voltmeter ................................................................................................................................................. HP 3480B/3484A
Oscilloscope ..............................................................................................................................................HP 180A/1801A/1820C
Initial Test Conditions
Top and bottom covers removed (see Service Sheet F).
Procedure
Set the generator's controls as listed in the box at the right-hand side of the diagram. To check a voltage at a test point, change
the control settings as specified in the box associated with that test point, check the voltage, then reset the controls to the settings
specified in the box at the right-hand side.
The blocks are keyed, by the numbers located in their lower right-hand corners, to the Service Sheets that have the circuit
schematics.
NOTE
The last two foldouts in this manual have top and bottom internal views of the instrument that show the
locations of the test points, assemblies, and cables (all RF cables are accessible from the bottom of the
instrument).
NOTE
After repairs are complete, see Table 5-2 for appropriate post-repair tests and adjustments.
AM/AGC Circuits and Output Amplifier Troubleshooting
SERVICE SHEET 3
8-24
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com