Artesyn Embedded Technology 6806800R89E, Assembly, Installation And Use

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SharpMedia PCIE-8120 Hardware Description
SharpMedia™ PCIE-8120 Installation and Use (6806800R89F )
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B.9.6 DSP 25MHz Clock Synchronization
The SharpMedia PCIE-8120 card provides clock synchronization for the entire DSP array to
ensure equal processing time on computing tasks that are shared between two or more DSP
units. The synchronized main DSP operating clock is 25 MHz.
DSPx_USER_HW_CONF[
3:0] HW Strapping DSP position on Mezzanine set by strapping
resistors range 0 - 11
0000 = DSP0
0001 = DSP1
0010 = DSP2
0011 = DSP3
0100 = DSP4
0101 = DSP5
0110 = DSP6
0111 = DSP7
1000 = DSP8
1001 = DSP9
1010 = DSP10
1011 = DSP11
DSPx_USER_HW_CONF[
7:4] BASE_ID[3:0] A card specific 4bit Base ID can be
programmed via the CPLD
DSPx_USER_HW_CONF[
13:8] HW Strapping Strapped by resistor to 1
DSPx_USER_HW_CONF[
14] CPLD 0 = Unique factory-burned per-chip MAC
address
1 = TFTP server with IP derived from
00:0C:90:02:<USER_HW_CONFIG>xx
DSPx_USER_HW_CONF[
15] CPLD 0 = TFTP server at 192.168.1.200
1 = TFTP server with IP derived from
192.168.<USER_HW_CONFIG>xx
BOOT_MODE[3:0] HW Strapping Strapped by resistor to
0100 = BOOTP on EMAC 2 on SERDES 2
Table B-6 DSP Control Signals (continued)
Signal Group Controlled by Description