Artesyn Embedded Technology 6806800R89E, Assembly, Installation And Use

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SharpMedia PCIE-8120 Hardware Description
SharpMedia™ PCIE-8120 Installation and Use (6806800R89F)
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B.9.3 Ethernet MAC Engines
The OCT2224M device on the PCIE-8120 card configures two Ethernet MAC engines,
supporting 10/100/1000-Mbps data transfer rates on the physical interfaces: SERDES2 and
SERDES3 in SGMII mode. See
Table B-5 below.
EMAC0 and EMAC2 support jumbo packets (maximum size of 9,018 bytes or 9,022 bytes for
VLAN frames). EMAC2 is available for BOOTP.
B.9.4 Boot Controller
The boot controller is responsible for managing the boot process. The boot process loads a
boot image that is created by an Octasic software tool that allows the user to specify optional
device configuration and the application image to load.
The boot process uses a default device configuration determined by either a lowest common
capability and/or the BOOT_MODE to load a boot image. The final device configuration
information is obtained from the boot image and can override the one used for the boot
process.
The SharpMedia PCIE-8120 card is configured for BOOTP on EMAC 2 on SERDES 2 (SGMII,
1Gbps).
B.9.5 DSP Configuration
The following table lists the assignment of the DSP control and configuration pins:
Table B-5 Ethernet Physical Interface Mapping
Mode SERDES0 SERDES1 SERDES2 SERDES3 Eth0 Eth1
5 EMAC 1 (not used) EMAC 3 (not used) EMAC 2 EMAC 0 n/a n/a
Table B-6 DSP Control Signals
Signal Group Controlled by Description
DSPx_RST_N CPLD Reset input to each DSP
DSPx_INT_N CPLD Interrupt output from each DSP