Arm® Corstone™ SSE
-300 with Cortex®-
M55 and Ethos™
-U55 :
Example Subsystem for MPS3 - Application Note AN547
DAI 0547C
Issue C
4 Programmers Model
Copyright
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2020, 2021 Arm Limited (or its affiliates). All rights reserved.
Non-Confidential
Page 28 of 64
4
Programmers Model
This programmers model is supplemental to the CMSDK, SIE-200 and SIE-300
documentation which covers many
of the included components in more detail. The connectivity of the system is shown in MPS3 System Overview
Diagram.
4.1
ITCM
The primary boot memory is an ITCM which is implemented with 512KB of FPGA SRAM connected to the ITCM
interface of the Cortex-M55 inside the subsystem.
•
Size: 512KB FPGA SRAM
•
Address Range: 0x0000_0000 - 0x0007_FFFF
•
Alias Range: 0x1000_0000 - 0x1007_FFFF
4.2
FPGA SRAM
The code memory is extended with 2MB of internal FPGA SRAM.
•
Size: 2MB FPGA SRAM
•
Address Range: 0x0100_0000 - 0x011F_FFFF
•
Alias Range: 0x1100_0000 - 0x111F_FFFF
4.3
DTCM
The primary data memory is provided by DTCM made up of 4 banks, each implemented as 128KB of internal
FPGA SRAM connected to the 4 DTCM interfaces of the Cortex-M55 inside the subsystem.
•
Size: 4 x 128KB FPGA SRAM
•
Address Range: 0x2000_0000 - 0x2007_FFFF
•
Alias Range: 0x3000_0000 - 0x3007_FFFF
4.4
QSPI
The SMM provides 8MB of external Flash memory which is accessed through a QSPI interface.
•
Size: 8MB fitted
•
Address Range: 0x2800_0000 - 0x287F_FFFF
•
Alias Range: 0x3800_0000 - 0x387F_FFFF
4.5
DDR4
The SMM provides access to 2GB of External DDR4 memory through the DDR4 controller.
•
Size: 2GB DDR4 (4GB fitted only 2GB accessible)
•
Address Range: 0x6000_0000 - 0xDFFF_FFFF
