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Arm® Corstone™ SSE

-300 with Cortex®-

M55 and Ethos™

-U55 :

Example Subsystem for MPS3 - Application Note AN547

DAI 0547C

Issue C

3 Overview

Copyright

©

2020, 2021 Arm Limited (or its affiliates). All rights reserved.

Non-Confidential

Page 27 of 64

3.9

FPGA Utilization

This application note is designed for MPS3 board. The board will use a a Xilinx Kintex Ultrascale XCKU115 FPGA. The FPGA
features up to 8MB BRAM (2160 BlocRAM tiles) and up to 663360 LUTs.
Full part number: XCKU115-FLVB1760-1-C.

3.9.1

Total design utilization

The following table shows the total number of LUTs and BRAMs currently used in the provided image.

Site Type

Used

Util%

LUTs

270540

40

BlockRAM Tile

1851

86

Note :

These numbers relate to the complete image, not individual IP blocks. The numbers must not be used to infer IP

size, or the relative sizes of different IP blocks, because the implementation and system design can significantly differ.

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Summary of Contents for Corstone SSE-300

Page 1: ...stone SSE 300 with Cortex M55 and Ethos U55 Example Subsystem for MPS3 Revision C Application Note AN547 Non Confidential Issue C Copyright 2020 2021 Arm Limited or its affiliates All rights reserved DAI 0547C ...

Page 2: ...ANTABILITY SATISFACTORY QUALITY NON INFRINGEMENT OR FITNESS FOR A PARTICULAR PURPOSE WITH RESPECT TO THE DOCUMENT For the avoidance of doubt Arm makes no representation with respect to and has undertaken no analysis to identify or understand the scope and content of patents copyrights trade secrets or other rights This document may include technical inaccuracies or typographical errors TO THE EXTE...

Page 3: ...red in England 110 Fulbourn Road Cambridge England CB1 9NJ LES PRE 20349 Confidentiality Status This document is Non Confidential The right to use copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to Unrestricted Access is an Arm internal classification Product Stat...

Page 4: ...art A Hardware Binaries Encrypted FPGA bitstream file containing various the Arm technology including SSE 300 Subsystem Cortex M55 Processor Ethos U55 Embedded ML Inference processor Software Binaries Motherboard Configuration Controller binary mbb_vxxx ebf including Keil USB and SD card drivers and Analog Devices FMC EEPROM reader selftest binary an547_st axf for Cortex M55 in Corstone SSE 300 Do...

Page 5: ...her information 11 2 Preface 12 2 1 Purpose of this application note 12 2 2 Terms and abbreviations 12 2 3 Arm IP version details 13 2 4 Encryption key 13 3 Overview 14 3 1 System block diagram 14 3 2 SSE 300 Configuration 15 3 2 1 Render Settings 15 3 2 2 Subsystem static input values 17 3 3 SIE 300 Components 18 3 4 SIE 200 Components 18 3 5 CoreLink XHB 500 18 3 6 Memory Protection 18 3 7 Memor...

Page 6: ...et 31 4 12 USB 31 4 13 RTC 31 4 14 Audio I2 S 32 4 15 Audio Configuration 33 4 16 FPGA system control and I O 34 4 17 Serial Configuration Controller SCC 35 5 Clock architecture 37 5 1 Clocks 37 5 1 1 Source clocks 37 5 1 2 Generated clocks 37 5 1 3 SSE 300 clocks 38 6 FPGA Secure Privilege Control 39 7 Interrupt Map 43 7 1 UART Interrupts 45 8 Shield Support 46 9 ZIP Bundle Description 48 9 1 Ove...

Page 7: ...age onto the MPS3 Board 51 11 3 UART Serial Ports 52 11 4 UART Serial Port Terminal Emulator Settings 52 11 5 MPS3 USB Serial port drivers for Windows 52 11 6 MCC Memory mapping 53 12 Software 54 12 1 Rebuilding software 54 12 2 Loading software on the MPS3 board 54 13 Debug 55 13 1 Debug Connectivity 55 13 2 Debug support for Keil MDK 55 13 3 Trace support for Keil MDK 57 13 4 Debug and Trace sup...

Page 8: ... experience with Arm products Such engineers typically have experience in writing Verilog and of performing synthesis but might have limited experience of integrating and implementing Arm products 1 2 Conventions The following subsections describe conventions used in Arm documents 1 2 1 Glossary The Arm Glossary is a list of terms used in Arm documentation together with definitions for those terms...

Page 9: ...sembler syntax where they appear in code or code fragments For example MRC p15 0 Rd CRn CRm Opcode_2 SMALL CAPITALS Used in body text for a few terms that have specific technical meanings that are defined in the Arm Glossary For example IMPLEMENTATION DEFINED IMPLEMENTATION SPECIFIC UNKNOWN and UNPREDICTABLE This represents a recommendation which if not followed might lead to system failure or dam...

Page 10: ...0571 No Arm CoreLink SIE 300 AXI5 System IP for Embedded Technical Reference Manual 101526 No Arm Cortex M System Design Kit Technical Reference Manual DDI 0479 No Arm CoreLink XHB 500 Bridge Technical Reference Manual 101375 No MCBQVGA TS Display v12 Keil MCBSTM32F200 display board schematic No Arm MPS3 FPGA Prototyping Board Getting Started Guide No Table 1 1 Arm Publications 1 4 Feedback Arm we...

Page 11: ...gestions for additions and improvements 1 4 3 Other information Arm Documentation https developer arm com documentation Arm Technical Support Knowledge Articles https www arm com support technical support Arm Support https www arm com support Arm Glossary https developer arm com documentation aeg0014 g The Arm Glossary is a list of terms used in Arm documentation together with definitions for thos...

Page 12: ... abbreviations AHB Advanced High performance Bus APB Advanced Peripheral Bus BRAM Block Random Access Memory CMSDK Cortex M System Design Kit DMA Direct Memory Access DTCM Data Tightly Coupled Memory EAM Exclusive Access Controller FPGA Field Programmable Gate Array IDAU Implementation Defined Attribution Unit ITCM Instruction Tightly Coupled Memory KB Kilobyte MB Megabyte MCC Motherboard Configur...

Page 13: ...he CoreLink SIE 200 System IP for Embedded product is a collection of interconnect peripheral and TrustZone controller components for use with a processor that complies with the ARMv8 M processor architecture BP210 Cortex M System Design Kit Full version of the design kit supporting Cortex M0 Cortex M0 DesignStart Cortex M0 Cortex M3 and Cortex M4 Also contains the AHB Bus Matrix and advanced AHB ...

Page 14: ...ubsystem_1 mps3_core_apb_subsystem_0 mps3_core_mem_wrapper mps3_core_mem_mpc_ppc Trace Port JTAG Port Ethernet LCD Shield PMOD 0 1 TSC Audio Switches Buttons LEDs ADC QSPI flash MCC DDR4 AXI5 MPC AHB to APB APB PPC APB PPC AHB to APB AHB PPC AXI5 MPC APB APB AHB5 to AHB lite NIC400 AXI5 MPC APB APB SMB TO AHB clocks resets mps3_bram_qspi_memsubsys Default Slave AHB GPIO x4 UART x6 SPI x3 master Au...

Page 15: ... 0 0 CPU3TYPE 0 0 NUMNPU 1 1 NPU0TYPE 1 1 NPU1TYPE 0 0 NPU2TYPE 0 0 NPU3TYPE 0 0 NPU0_NUM_MACS 128 128 NPU1_NUM_MACS 256 256 NPU2_NUM_MACS 32 32 NPU3_NUM_MACS 64 64 NUM_AXI_SLAVES_EXP_MI 2 2 NUM_AHB_SLAVES_EXP_PIHL 1 1 NUM_AHB_SLAVES_EXP_PILL 1 1 EXPLOGIC_PRESENT 1 1 VMMPCBLKSIZE 7 11 CPU0_INITNSVTOR_ADDR_INIT 0x00000000 0x00000000 CPU0EXPNUMIRQ 64 100 CPU0EXPIRQDIS 64b0 100b0 CPU0_EXP_IRQTIER 65b...

Page 16: ...ROMVALID 1 1 SOCVAR 0x0 0x0 SOCREV 0x0 0x0 SOCPRTID 0x7E0 0x7E0 SOCIMPLID 0x43B 0x43B IMPLVAR 0x0 0x0 IMPLREV 0x0 0x0 IMPLPRTID 0x74A 0x74A IMPLID 0x43B 0x43B INITTCMEN 0b11 0b11 INITPAHBEN 1 1 LOCKDCAIC 0 0 TCM_MID_WIDTH 5 5 S_MID_WIDTH 5 6 TCM_ID_WIDTH 5 5 XS_ID_WIDTH 6 6 S_HMASTER_WIDTH 5 4 XOM_USER_SIGNAL_PRESENT 0 0 CPU0_PMC_PRESENT 0 0 NUMVMBANK 2 2 VMADDRWIDTH 18 21 HASCRYTO 0 0 HASCSS 0 0 ...

Page 17: ...ATION_SCHEME round round CPU0_CFGPAHBZE 0b010 0b010 CPU0_LOCKPAHB 1 1 PERFORM_CONFIGCHECK 1 1 Table 3 1 SSE 300 Render Configuration Settings 3 2 2 Subsystem static input values The SSE 300 subsystem in AN547 has several inputs which are tied off and therefore static at the subsystem top level These are detailed in the below table Input Tie Off Value CPU0_INITSVTOR 1 25 h0200000 CPU0CFGFPU 1 b1 CP...

Page 18: ...00 Components This system uses the following SIE 200 components TrustZone AHB5 peripheral protection controller TrustZone AHB5 Manager security controller AHB5 bus matrix AHB5 to AHB5 synchronous bridge AHB5 to APB synchronous bridge TrustZone APB4 peripheral protection controller AHB5 default subordinate 3 5 CoreLink XHB 500 This system implements one CoreLink XHB 500 configured for AHB to AXI mo...

Page 19: ...CM 512KB I2C DDR4 EEPROM Reserved Reserved Arm v8 M Ref Memory map AN547 Memory map 0x0100_0000 QSPI 8MB Reserved ITCM 512KB 0x2100_0000 0x2880_0000 DTCM 4 x 128KB Reserved Reserved Secure Low Latency Peripheral Region Reserved Subsystem Peripherals 0x4010_0000 0x4000_0000 USER AHB 0 0x4110_5000 USER AHB 1 0x4110_6000 USER AHB 2 0x4110_7000 USER AHB 3 0x4110_8000 0x4120_0000 DMA 0 0x4120_1000 DMA ...

Page 20: ...0 0x213F_FFFF 4MB SRAM Internal SRAM Area SSE 300 implements 2x2MB 3 17 12 0x2140_0000 0x27FF_FFFF 108MB Reserved Reserved 13 0x2800_0000 0x287F_FFFF 8MB SRAM QSPI 8MB 1 19 14 0x2880_0000 0x2FFF_FFFF 120MB Reserved Reserved 15 0x3000_0000 0x303F_FFFF 512KB SRAM DTCM 4 x banks of 128KB 3 9 S 3 RAM NSC 16 0x3040_0000 0x30FF_FFFF 15 5MB Reserved Reserved 17 0x3100_0000 0x313F_FFFF 4MB SRAM Internal S...

Page 21: ...xDFFF_FFFF 256MB External device DDR41 S D 0 33 0xE000_0000 0xE00F_FFFF 1MB EPPB External Private Peripheral Bus Exempt 34 0xE010_0000 0xE01F_FFFF 1MB Vendor_SYS Reserved NS E 0 35 0xE020_0000 0xEFFF_FFFF 254MB Vendor_SYS Maps to HMSTEXPPILL Expansion Interface2 NS E 0 36 0xF000_0000 0xF00F_FFFF 1MB Vendor_SYS Reserved Exempt 37 0xF010_0000 0xF01F_FFFF 1MB Vendor_SYS Reserved S F 0 38 0xF020_0000 ...

Page 22: ...erals to Secure or Non secure address space all peripherals are mapped twice and either an APB PPC or an AHB PPC gates access to these peripherals 3 8 1 Manager Peripheral Expansion Low Latency Interface Memory Map HMSTEXPPILL The following table shows the FPGA peripheral mapping to the Non secure Low Latency region ROW ID Address Size Description Alias with ROW ID Port From To 1 0x4000_0000 0x400...

Page 23: ...00 0x5110_0FFF 4KB GPIO 0 3 AHB 31 0x5110_1000 0x5110_1FFF 4KB GPIO 1 4 32 0x5110_2000 0x5110_2FFF 4KB GPIO 2 5 33 0x5110_3000 0x5110_3FFF 4KB GPIO 3 6 34 0x5110_4000 0x5110_4FFF 4KB AHB USER 0 7 35 0x5110_5000 0x5110_5FFF 4KB AHB USER 1 8 36 0x5110_6000 0x5110_6FFF 4KB AHB USER 2 9 37 0x5110_7000 0x5110_7FFF 4KB AHB USER 3 10 38 0x5110_8000 0x511F_FFFF Reserved 39 0x5120_0000 0x5120_0FFF Reserved...

Page 24: ...2021 Arm Limited or its affiliates All rights reserved Non Confidential Page 24 of 64 ROW ID Address Size Description Alias with ROW ID Port From To 57 0x5700_2000 0x5700_2FFF 4KB DDR4 Memory Protection Controller MPC 58 0x5700_3000 0x57FF_FFFF Reserved Table 3 3 MSTEXPPILL Secure Peripheral Map Reserved regions respond with RAZ WI when accessed ...

Page 25: ...x4920_3FFF 4KB FPGA PL022 SPI Shield0 38 11 0x4920_4000 0x4920_4FFF 4KB FPGA PL022 SPI Shield1 39 12 0x4920_5000 0x4920_5FFF 4KB SBCon I2C Shield0 40 13 0x4920_6000 0x4920_6FFF 4KB SBCon I2C Shield1 41 14 0x4920_7000 0x4920_7FFF 4KB USER APB 42 15 0x4920_8000 0x4920_8FFF 4KB FPGA SBCon I2C DDR4 EEPROM 43 16 0x4920_9000 0x492F_FFFF Reserved 17 0x4930_0000 0x4930_0FFF 4KB FPGA SCC registers 45 APB1 ...

Page 26: ...20_4FFF 4KB FPGA PL022 SPI Shield1 11 40 0x5920_5000 0x5920_5FFF 4KB SBCon I2C Shield0 12 41 0x5920_6000 0x5920_6FFF 4KB SBCon I2C Shield1 13 42 0x5920_7000 0x5920_7FFF 4KB USER APB 14 43 0x5920_8000 0x5920_8FFF 4KB FPGA SBCon I2C DDR4 EEPROM 15 44 0x5920_9000 0x592F_FFFF Reserved 45 0x5930_0000 0x5930_0FFF 4KB FPGA SCC registers 17 APB1 46 0x5930_1000 0x5930_1FFF 4KB FPGA I2S Audio 18 47 0x5930_2...

Page 27: ...le XCKU115 FPGA The FPGA features up to 8MB BRAM 2160 BlocRAM tiles and up to 663360 LUTs Full part number XCKU115 FLVB1760 1 C 3 9 1 Total design utilization The following table shows the total number of LUTs and BRAMs currently used in the provided image Site Type Used Util LUTs 270540 40 BlockRAM Tile 1851 86 Note These numbers relate to the complete image not individual IP blocks The numbers m...

Page 28: ...000_0000 0x0007_FFFF Alias Range 0x1000_0000 0x1007_FFFF 4 2 FPGA SRAM The code memory is extended with 2MB of internal FPGA SRAM Size 2MB FPGA SRAM Address Range 0x0100_0000 0x011F_FFFF Alias Range 0x1100_0000 0x111F_FFFF 4 3 DTCM The primary data memory is provided by DTCM made up of 4 banks each implemented as 128KB of internal FPGA SRAM connected to the 4 DTCM interfaces of the Cortex M55 insi...

Page 29: ... SPI interface on each header These are alt functions on the GPIO ports See Shield Support Section for mappings 4 8 SBCon I2 C The SMM implements five SBCon serial modules One SBCon module for use by the Color LCD touch interface One SBCon module to configure the audio controller Two general purpose SBCon modules that connect to Shield0 and Shield1 and provide an I2 C interface on each header Thes...

Page 30: ...y board See MCBQVGA TS Display v12 Keil MCBSTM32F200 display board schematic The Keil display board contains an AM240320LG display panel and uses a Himax HX8347 D LCD controller The selftest software provided with the MPS3 includes drivers and example code for both interfaces The following table lists CLCD control and data registers in offset order from the base memory address The CLCD non secure ...

Page 31: ...te of Access Complete ANDed with the CHAR_MASK 0x04C CHAR_MISC Miscellaneous Control Bit Field Description Bits 31 7 Reserved Bit 6 CLCD_BL Bit 5 CLCD_RD Bit 4 CLCD_RS Bit 3 CLCD_RESET Bit 2 RESERVED Bit 1 CLCD_WR Bit 0 CLCD_CS Table 4 3 LCD control and data registers 4 11 Ethernet The SMM design connects to an SMSC LAN9220 device through a static memory interface The selftest software includes ex...

Page 32: ...t 11 Reserved Bits 10 8 TX Buffer IRQ Water Level Default 2 IRQ triggers when more than two word space is available Bits 7 4 Reserved Bit 3 Rx Interrupt Enable Bit 2 Rx Enable Bit 1 Tx Interrupt Enable Bit 0 Tx Enable 0x004 STATUS Status Register Bits 31 6 Reserved Bit 5 Rx Buffer Full Bit 4 Rx Buffer Empty Bit 3 Tx Buffer Full Bit 2 Tx Buffer Empty Bit 1 Rx Buffer Alert Depends on Water level Bit...

Page 33: ...TCR Integration Test Control Register Bits 31 1 Reserved Bit 0 ITCR 0x304 ITIP1 Integration Test Input Register 1 Bits 31 1 Reserved Bit 0 SDIN 0x308 ITOP1 Integration Test Output Register 1 Bits 31 4 Reserved Bit 3 IRQOUT Bit 2 LRCK Bit 1 SCLK Bit 0 SDOUT Table 4 4 Audio I2S Register Map 4 15 Audio Configuration The SMM implements a simple SBCon interface based on I2 C It configures the Cirrus Lo...

Page 34: ...ved Bit 3 SPNIDEN Bit 2 SPIDEN Bit 1 NIDEN Bit 0 DBGEN 0x008 FPGAIO BUTTON Buttons Bits 31 2 Reserved Bits 1 0 Buttons 0x00C FPGAIO GPIOALT2 GPIO Alt Function 2 select Bits 31 0 Reserved 0x010 FPGAIO CLK1HZ 1Hz up counter 0x014 FPGAIO CLK100HZ 100Hz up counter 0x018 FPGAIO COUNTER Cycle Up Counter Increments when 32 bit prescale counter equals zero and automatically reloads 0x01C FPGAIO PRESCALE P...

Page 35: ...esses and write addresses of the SCC interface do not use bits 1 0 All address words are word aligned The following table shows SCC registers in offset order from the base address The non secure base address in 0x49300000 the secure is 0x59300000 Address Name Information 0x000 CFG_REG0 Bits 31 2 Reserved Bit 1 CPU_WAIT ctrl Bit 0 Reserved 0x004 CFG_REG1 Bits 31 0 DATA RW 0x008 CFG_REG2 Bits 31 1 R...

Page 36: ...ted clocks 0x0AC SYS_CFGSTAT Bits 31 2 Reserved Bit 1 Error Bit 0 Complete 0x0B0 0xFF4 RESERVED 0xFF8 SCC_AID SCC AID register is read only Bits 31 24 FPGA build number Bits 23 20 V2M MPS3 target board revision A 0 B 1 C 2 Bits 19 8 Reserved Bits 7 0 Number of SCC configuration register 0xFFC SCC_ID SCC ID register is read only Bits 31 24 Implementer ID 0x41 Arm Bits 23 20 Reserved Bits 19 16 IP A...

Page 37: ...CLK 4 24 576MHz Programmable oscillator HDLCDCLK OSCCLK 5 23 75MHz Programmable oscillator DBGCLK CS_TCK Set by debugger JTAG input CFGCLK CFG_CLK Set by MCC SCC register clock from MCC DDR4_REF_CLK c0_sys_clk_p n 100MHz Differential input clock to DDR4 controller SMBM_CLK SMBM_CLK Set by MCC 40MHz SMB clock from MCC Table 5 1 Source clocks 5 1 2 Generated clocks The following clocks are generated...

Page 38: ...ghts reserved Non Confidential Page 38 of 64 5 1 3 SSE 300 clocks The following clocks generated within the FPGA are connected to the SSE 300 subsystem SSE 300 Clock Input FPGA Clock Frequency Note SYSCLK MAINCLK 32MHz Main System clock CPU0CLK MAINCLK 32MHz CPUclock AONCLK MAINCLK 32MHz Always On clock CNTCLK MAINCLK 32MHz Counter clock SLOWCLK CLK32KHZ 32KHz Slow clock Table 5 3 SSE 300 clocks ...

Page 39: ..._irq SPERIPHPPCEXPSTATUS 0 apb_ppc_clear SPERIPHPPCEXPCLEAR 0 APB PPC EXP 0 cfg_sec_resp SECRESPCFG cfg_non_sec PERIPHNSPPCEXP0 15 0 cfg_ap PERIPHPPPCEXP0 15 0 APB PPC EXP 1 apb_ppc_irq SPERIPHPPCEXPSTATUS 1 apb_ppc_clear SPERIPHPPCEXPCLEAR 1 cfg_sec_resp SECRESPCFG cfg_non_sec PERIPHNSPPCEXP1 15 0 cfg_ap PERIPHPPPCEXP1 15 0 APB PPC EXP 2 apb_ppc_irq SPERIPHPPCEXPSTATUS 2 apb_ppc_clear SPERIPHPPCE...

Page 40: ...n interface is controlled by PERIPHNSPPCEXP0 n and PERIPHPPPCEXP0 n APB PPC EXP 0 Interface Number n Name 0 USER MEM APB0 1 USER MEM APB0 3 2 Reserved 4 NPU APB0 5 NPU APB1 12 6 Reserved 13 SSRAM Memory Protection Controller MPC 14 QSPI Memory Protection Controller MPC 15 DDR4 Memory Protection Controller MPC Table 6 3 Peripherals Mapping of APB PPC EXP 0 The following table lists the peripherals ...

Page 41: ...PGA SCC registers 1 FPGA I2S Audio 2 FPGA IO System Ctrl I O 3 UART0 UART_F 0 4 UART1 UART_F 1 5 UART2 UART_F 2 6 UART3 UART Shield0 7 UART4 UART Shield1 8 UART5 UART_F 3 9 Reserved 10 CLCD 11 RTC 15 12 Reserved Table 6 5 Peripherals Mapping of APB PPC EXP 2 The following table lists the peripherals that are controlled by MAIN PPC EXP 0 Each APB n interface is controlled by MAINNSPPCEXP0 n and MAI...

Page 42: ...21 Arm Limited or its affiliates All rights reserved Non Confidential Page 42 of 64 The following table lists the peripherals that are controlled by MAIN PPC EXP 1 Each APB n interface is controlled by MAINNSPPCEXP1 n and MAINPPPCEXP1 n AHB PPC EXP 1 Interface Number n Name 0 Reserved 1 DMA 1 2 DMA 2 3 DMA 3 15 4 Reserved Table 6 7 Peripherals Mapping of AHB PPC EXP 1 ...

Page 43: ... 0 IRQ 4 Timer 1 IRQ 5 Timer 2 IRQ 6 Reserved IRQ 7 Reserved IRQ 8 Reserved IRQ 9 MPC Combined Secure IRQ 10 PPC Combined Secure IRQ 11 MSC Combined Secure IRQ 12 Bridge Error Combined Interrupt Secure IRQ 13 Reserved IRQ 14 MGMT_PPU IRQ 15 SYS_PPU IRQ 16 CPU0_PPU IRQ 17 Reserved IRQ 18 Reserved IRQ 19 Reserved IRQ 20 Reserved IRQ 21 Reserved IRQ 22 Reserved IRQ 23 Reserved IRQ 24 Reserved IRQ 25 ...

Page 44: ...1 Touch Screen IRQ 52 USB IRQ 53 SPI ADC IRQ 54 SPI Shield 0 IRQ 55 SPI Shield 1 IRQ 56 U55 Interrupt IRQ 59 57 Reserved IRQ 60 DMA 1 Error Interrupt IRQ 61 DMA 1 Terminal Count Interrupt IRQ 62 DMA 1 Combined Interrupt IRQ 63 DMA 2 Error Interrupt IRQ 64 DMA 2 Terminal Count Interrupt IRQ 65 DMA 2 Combined Interrupt IRQ 66 DMA 3 Error Interrupt IRQ 67 DMA 3 Terminal Count Interrupt IRQ 68 DMA 3 C...

Page 45: ...tial Page 45 of 64 7 1 UART Interrupts There are six CMSDK UARTs in the system each with the following interrupt pins TXINT RXINT TXOVRINT EXOVRINT UARTINT The TXINT RXINT and UARTINT interrupt signals of each UART drive a single interrupt input of the SSE 300 Example Subsystem In addition the TXOVERINT and EXOVRINT interrupt signals of all six UARTs twelve signals in all are logically ORed togeth...

Page 46: ... Shield Device Expansion Multiplexing is controlled by the alternative function output from the associated GPIO Register An experimental second alternative function is multiplexed for pins 1 9 of Shield 0 and these are controlled through GPIOALT2 in the FPGAIO Registers at address offset 0x0C The second ALT function is unused on AN547 and is not shown in the following table MPS3 GPIO ALT Function ...

Page 47: ...d 0 I2C Data SH0_IO15 GPIO0_15 SBCON2 SCL SH0_SCL Shield 0 I2C Clock SH1_IO0 GPIO1_0 UART4 RXD SH1_RXD Shield 1 UART Receive SH1_IO1 GPIO1_1 UART4 TXD SH1_TXD Shield1 UART Transmit SH1_IO2 GPIO1_2 SH1_IO3 GPIO1_3 SH1_IO4 GPIO1_4 SH1_IO5 GPIO1_5 SH1_IO6 GPIO1_6 SH1_IO7 GPIO1_7 SH1_IO8 GPIO1_8 SH1_IO9 GPIO1_9 SH1_IO10 GPIO1_10 SPI4 SS SH1_nCS Shield 1 SPI Chip Select SH1_IO11 GPIO1_11 SPI4 MOSI SH1_...

Page 48: ...rsion 5 31 software project that can be run on the MPS3 board peripherals and interfaces Boardfiles directory containing the directory structure and files to be loaded onto the MPS3 SD Card This is required to configure the MPS3 board to load and run this implementation 9 2 Bundle Directory Tree Structure The directory tree structure of the bundle is shown below Boardfiles MB HBI0309B HBI0309C SOF...

Page 49: ...547 DAI 0547C Issue C 8 Shield Support Copyright 2020 2021 Arm Limited or its affiliates All rights reserved Non Confidential Page 49 of 64 apssp aptimer aptsc apuart apusb RTE v2m_mps3 an547_st axf move bat selftest_mpb uvoptx selftest_mpb uvprojx Licence pdf Release_Notes txt revision_history txt ...

Page 50: ...identifier In this picture the part number is HBI0309B which indicates that the board is revision B 10 2 Bundle support for specific MPS3 board revisions There are two subdirectories in the Boardfiles MB directory that correspond to the two supported revisions HBI0309B HBI0309C The contents of each of these directories within the provided zip bundle are identical but the MCC only uses the contents...

Page 51: ... copy the contents of install_dir Boardfiles and paste them into the root directory of the attached V2M_MPS3 drive Note You might want to manually modify and merge the contents for certain configuration files Alternatively you can restore the existing configuration files from the Boardfiles directory The affected configuration files are a install_dir Boardfiles config txt b install_dir Boardfiles ...

Page 52: ...to the UART 1 Serial Port 3 is connected to the UART 2 The logical physical mapping of the Serial Ports on a host PC can be confusing due to the way the driver may allocate the port numbers The Serial Port presented with the lowest number aligns to Serial Port 0 above 11 4 UART Serial Port Terminal Emulator Settings All serial ports on this implementation use the following terminal serial port set...

Page 53: ...7_FFFF 0x0000_0000 0x0007_FFFF 512KB ITCM NS 0x0100_0000 0x011F_FFFF 0x6100_0000 0x6107_FFFF 0x1000_0000 0x1007_FFFF 512KB ITCM S 0x0200_0000 0x0207_FFFF 0x6200_0000 0x621F_FFFF 0x0100_0000 0x011F_FFFF 2MB FPGA SRAM NS 0x0300_0000 0x031F_FFFF 0x6300_0000 0x631F_FFFF 0x1100_0000 0x111F_FFFF 2 MB FPGA SRAM S 2 0x0400_0000 0x04FF_FFFF 0x6400_0000 0x64FF_FFFF 0x4100_0000 0x41FF_FFFF 16 MB Low Latency ...

Page 54: ...ftest an547_st axf 12 2 Loading software on the MPS3 board Requirements MPS3 board powered and USB cable connected MPS3 USB mass storage open in a file explorer The following instructions apply to all versions of software 1 Copy the software install_dir Software selftest an547_st axf to the board MPS3_dir Software folder 2 Navigate to MPS3_dir MB HBI0309C AN547 and open the images txt file in a te...

Page 55: ...ample Subsystem Technical Reference Manual 13 1 Debug Connectivity The following table shows the supported connectivity between the MPS3 Board debug connectors and the supported debug in the SMM See Figure 13 3 MPS3 Board Debug Connector Locations for the locations of the debug connectors on the board Debug Connector Type P JTAG Debug SWD 4 bit Trace 16 bit Trace 20 pin Cortex debug and ETM Yes Ye...

Page 56: ...55 and Ethos U55 Example Subsystem for MPS3 Application Note AN547 DAI 0547C Issue C 13 Debug Copyright 2020 2021 Arm Limited or its affiliates All rights reserved Non Confidential Page 56 of 64 Figure 13 1 Keil MDK debug configuration ...

Page 57: ...reserved Non Confidential Page 57 of 64 Apply the following debug settings if using CMSIS DAP Armv8 M Debugger Port SW Reset Autodetect Connect Normal Figure 13 2 Keil MDK debug configuration 13 3 Trace support for Keil MDK It is planned to include trace support for SSE 300 in future versions of the Keil Tool Please follow the announcements of tool and pack updates related to the platform ...

Page 58: ...s this provides the support for the subsystem in this implementation and was the version used for testing of this application note 13 4 1 Establishing a Debug Session To estalish a debug connection to the Cortex M55 processor follow these steps Steps 1 Ensure the Arm DSTREAM debug probe is a Powered and connected to the host running the Development Studio software b Connected to the MPS3 using the...

Page 59: ...ns dialog box by right clicking in the Debug Control window and selecting debug configurations This will open the debug configuration window a Double left click on the Generic Arm C C application this will create a new configuration b In the connection tab in the search bar enter MPS3 and select the Cortex M55 under Cortex M Prototyping System MPS3 Cortex M55 SSE 300 Subsystem as shown in the exam...

Page 60: ...Application Note AN547 DAI 0547C Issue C 13 Debug Copyright 2020 2021 Arm Limited or its affiliates All rights reserved Non Confidential Page 60 of 64 c Next in the Debugger tab make sure that the run control is set to Connect only Figure 13 5 Arm DS debug configurations Debugger ...

Page 61: ... a connection to the DSTREAM needs to be setup To do this select the connection tab select Browse highlighted in red a new window will open giving a list of all possible DSTREAM s Choose your DSTREAM and click select highlighted in blue Figure 13 6 Arm DS connection browser e Now click the Apply button followed by the Debug button to start your debug session 3 Program execution at this stage can b...

Page 62: ...or its affiliates All rights reserved Non Confidential Page 62 of 64 13 4 2 Trace in Debug session Follow steps in section 13 4 1 and before step 2 e implement the following steps 1 Click the Edit button next to DTSL Options shown below Connect the debug probe to either 20 pin IDC Mictor 38 for trace to work Figure 13 7 Arm DS debug configurations DTSL Options ...

Page 63: ... Subsystem for MPS3 Application Note AN547 DAI 0547C Issue C 13 Debug Copyright 2020 2021 Arm Limited or its affiliates All rights reserved Non Confidential Page 63 of 64 2 A new window will open on the first tab select DSTREAM 4GB Trace Buffer as shown below ...

Page 64: ...ystem for MPS3 Application Note AN547 DAI 0547C Issue C 13 Debug Copyright 2020 2021 Arm Limited or its affiliates All rights reserved Non Confidential Page 64 of 64 3 On the Cortex M55 tab check the Enable Cortex M55 core trace box and then click Apply and then OK ...

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