AMD SP5100 Data Book Download Page 79 | Manualshive

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AMD SP5100 Data Book Download Page 79

44409

Rev.

1.70

October 10

AMD SP5100 Databook

Testability

79

Table 14-4: Truth Table for an XOR Chain

Test Vector

number

Input Pin G Input Pin F

Input Pin E Input Pin D Input Pin C Input Pin B Output Pin A

1

0

0

0

0

0

0

1

2

1

0

0

0

0

0

0

3

1

1

0

0

0

0

1

4

1

1

1

0

0

0

0

5

1

1

1

1

0

0

1

6

1

1

1

1

1

0

0

7

1

1

1

1

1

1

1

14.2.2 Description of the SP5100 XOR Chain

During XOR Chain Test Mode, most of the chip pads on the SP5100 are connected together
using XOR gates as shown in Figure 14-3. The first input of the chain is connected to a logic level
high (internal connection), and all pads (listed in Table 14-5) are configured as inputs except for
the last pad in the chain, which is configured as an output.

KBRST#/GEVENT1#

is the start of the

chain and

SERIRQ

is the end of the chain. Table 14-5 lists all pads that are on the SP5100 XOR

chain, as well as and their order of connection. Pads are chained together in the shown order,
i.e., pad number 1 is the first pad on the XOR chain, pad number 2 the second, and so on.

1 ( Tie high Internal to Asic)

pin 1

AD6/ROMA12

pin 2

pin 3

pin N

Frame#

XOR out

FANOUT0/ GPIO3

Figure 14-3: On-chip XOR Chain connectivity

Table 14-5: List of Pins on the SP5100 XOR Chain and the Order of Connection

XOR #

Pin Name

1

KBRST#/GEVENT1#

2

GA20IN/GEVENT0#

3

NB_PWRGD

4

SATA_ACT#/GPIO67

5

LDRQ1#/GNT5#/GPIO68

6

AD20

7

CBE2#

8

REQ2#

9

BMREQ#/REQ5#/GPIO65

10

REQ4#/GPIO71

11

GNT3#/GPIO72

12

CLKRUN#

13

REQ3#/GPIO70

XOR #

Pin Name

14

GNT4#/GPIO73

15

INTF#/GPIO34

16

REQ1#

17

GNT1#

18

INTE#/GPIO33

19

INTH#/GPIO36

20

GNT0#

21

INTG#/GPIO35

22

AD31

23

GNT2#

24

REQ0#

25

AD29

26

AD30

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Summary of Contents for SP5100

Page 1: ...Technical Reference Manual Rev 1 70 P N 44409_sp5100_ds_pub 2010 Advanced Micro Devices Inc AMD SP5100 Databook...

Page 2: ...e whether express implied arising by estoppel or otherwise to any intellectual property rights are granted by this publication Except as set forth in AMD s Standard Terms and Conditions of Sale AMD as...

Page 3: ...d SBPWRGD corrected condition for GPIO IMC_GPIO and IDE pins VOH to IOH 8 0mA Updated Table 14 5 List of Pins on the SP5100 XOR Chain and the Order of Connection Corrected pin names at XOR 113 and 114...

Page 4: ...33 35 7 7 Serial ATA Interface 36 7 8 HD Audio Interface 37 7 9 Real Time Clock Interface 37 7 10 Hardware Monitor 37 7 11 SPI ROM Interface 38 7 12 Northbridge Power Management Interface 38 7 13 SMBu...

Page 5: ...em Clock AC Specifications 62 10 States of Power Rails during ACPI S1 to S5 States 66 11 Electrical Characteristics 67 11 1 Absolute Maximum Ratings 67 11 2 Functional Operating Range for Signal Input...

Page 6: ...0 Figure 4 2 Type II Straps Capture timing 20 Figure 4 3 Type I Straps Capture timing 21 Figure 6 1 SP5100 Ball out Assignment Left 31 Figure 6 2 SP5100 Ball out Assignment Right 32 Figure 8 1 SP5100...

Page 7: ...k AC Specifications 64 Table 9 6 LPC Clock AC Specifications 64 Table 9 7 PCI Clock AC Specifications 64 Table 9 8 PCI Express Clock AC Specifications 65 Table 9 9 RTC 32 KHz Output Clock AC Specifica...

Page 8: ...errupt steering supported for plug n play devices BIOS Hardware support to hide PCI device Spread spectrum support USB Controllers 5 OHCI and 2 EHCI Host controllers to supports 12 USB 2 0 ports and 2...

Page 9: ...odes 32x32 byte buffers each channel for buffering Swap bay support by tri state IDE signals Integrated IDE series resistor High Definition Audio 4 Independent output streams DMA 4 Independent input s...

Page 10: ...r 10 10 Introduction DIPM on SATA Note Advanced Power Management APM is not supported Hardware Monitor Hardware monitoring support for voltage sensors fan control and digital TSI to AM3 processors Not...

Page 11: ...te 2 YYWW ENG 218 0660013 SB700S A14 Note 6 Note 7 Figure 1 1 SP5100 Rev A14 Branding Diagram Note 1 Marketing logo Note 2 AMD product type Note 3 Date Code YYWW YY assembly start year WW assembly sta...

Page 12: ...0660026 SOUTHBRIDGE Note 1 Marketing logo Note 2 AMD product type Note 3 Date Code YYWW YY assembly start year WW assembly start week Note 4 COO Country of origin assembly site Note 5 This is wafer fo...

Page 13: ...N GPM 9 0 TEMPDEAD TEMPCAUT SHUTDOWN DC_STOP SCIOUT SOFF INT H A LDTRST RESET PWRGOOD A LINK B LINK PICD 0 RTC_IRQ PIDE_INTRQ USB_IRQ SATA_IRQ AZ_IRQ X1 X2 12 USB2 0 2 USB1 1 PORTS SERIRQ 6 PCI SLOTS...

Page 14: ...internal delay of the SB The system board design may add additional delay due to loading and trace length The acceptable delay including system layout loading is 1 ms maximum T7A 50 ms SB PWR_GOOD ri...

Page 15: ...ower rails SB PWR _ GOOD A_RST S0 STRAPS KBRST T8B PCIRST PCIE_ RCLKP N T2 PCICLK 5 0 See Note1 NB_ PWRGD T7 T7A LDT_PG See Note5 T11 T8A T9 T9A LDT_STP Note8 Wake Event SLP_S5 SLP_S3 T13 T8D LDT_RST...

Page 16: ...S0 power rails SB PWRGOOD A_RST KBRST T8B PCIRST T10 PCIE_RCLKP N PCICLK 5 0 NB_PWRGD T7 T7A LDT_PG See Note 5 T11 T8A T9 T9A LDT_STP Note 8 Wake Event SLP_S3 T13 T8D LDT_RST ALLOW_LDTSTP WAKE PWR_BTN...

Page 17: ...ng of SB PWR_GOOD the latching of strap will occur at approximately 10ms after the rising edge of SB PWR_GOOD Note 4 Typical time between A_RST and PCIRST is 75 ns The measurement should be done at 10...

Page 18: ...tate transition because G3 state is where both signals are inactivated SB PWR_GOOD T14 RSMRST S0 to G3 Figure 3 4 Timing for SB PWR_GOOD De asserted to RSMRST De asserted Note 11 On first power up G3...

Page 19: ...D SP5100 Databook SP5100 Power on Sequence and Timing 19 Note 12 The S5_3 3V ramp down should be controlled to achieve a slew rate of 8mV S or lower S5_3 3V Min Slew Rate 8 mV S Figure 3 6 S5_3 3V Pow...

Page 20: ...on S5_1 2V STRAPs board PwrGood RsmRst VDD Straps Type I Straps I Capture Straps Type II Straps I Straps Type I Straps Type II Undefined Straps II Capture Straps II Don t care Figure 4 1 Straps Captur...

Page 21: ...age Debug straps should have provision for PU or PD so they can be configured to either option when required for debug purposes Table 4 1 and Table 4 2 show the function of every strap signal in the d...

Page 22: ...ler IMC 0 V disable IMC 3 3 V enable IMC PCI_ROM_BOOT II Booting from PCI memory 0 V disable PCI ROM boot Default 3 3 V enable PCI ROM boot Note This feature is for debug pupose only After a G3 S5 tra...

Page 23: ...Use REQ2 as Ide 50 MHz bypass clock Use REQ1 as Ide 33 MHz bypass clock 3 3 V Use internal PLL Ide Clk Default Internal PU of 15 k PCI_AD24 PCIE_EEPROM II A Link Express II core strap from I2C ROM ena...

Page 24: ...es PCI Express PCIE_CALRP External 562 1 tolerance Reference resistor for the Tx termination Pull down to VSS_PCIE PCIE_CALRN External 2 05 K 1 tolerance Reference resistor for the Rx termination Pull...

Page 25: ...tegrated 15 K Pull up REQ3 GPIO70 Integrated 15 K Pull up See GPIO section below REQ4 GPIO71 Integrated 15 K Pull up See GPIO section below BMREQ REQ5 GPIO65 External Pull up if used as REQ5 Pull up S...

Page 26: ...TEVNT0 Integrated 10 K Pull up PM2_Rg F5h Default Pull up enabled LPC_SMI EXTEVNT1 Integrated 8 2 K Pull up PM2_Rg F5h Default Pull up enabled SMBALERT THRMTRIP GEVENT2 Integrated 10 K Pull up PM2_Rg...

Page 27: ...F8h Default Pull down enabled GPIO CLK_REQ0 SATA_IS3 GPIO0 Integrated 10 K Pull down PM2_Rg E0h Default Pull down enabled SPKR GPIO2 Integrated 8 2 K Pull up PM2_Rg E0h Default Pull up Pull down not e...

Page 28: ...GPIO17 Integrated 27 Series PM2_Rg E4h Default Pull up Pull down not enabled IDE_D3 FC_ADQ3 GPIO18 Integrated 27 Series PM2_Rg E4h Default Pull up Pull down not enabled IDE_D4 FC_ADQ4 GPIO19 Integrat...

Page 29: ...8h Default Pull up enabled INTF GPIO34 Integrated 8 2 K Pull up PM2_Rg E8h Default Pull up enabled INTG GPIO35 Integrated 8 2 K Pull up PM2_Rg E8h Default Pull up enabled INTH GPIO36 Integrated 8 2 K...

Page 30: ...ult Pull up enabled REQ3 GPIO70 Integrated 15 K Pull up PM2_Rg F1h Default Pull up enabled REQ4 GPIO71 Integrated 15 K Pull up PM2_Rg F1h Default Pull up enabled GNT3 GPIO72 Integrated 8 2 K See Note...

Page 31: ...AVSS_USB_18 K SCL1 GPOC2 SDA1 GPOC3 SUS_STAT LPC_PME GE VENT3 VSS_8 AVSS_USB_21 VSS_9 AVSS_USB_22 L S5_3 3V_6 S5_3 3V_7 VSS_11 AZ_DOCK_RST GPM8 AZ_SYNC VSS_12 AZ_SDIN2 GPI O44 VDDQ_1 VSS_13 VSS_14 VS...

Page 32: ...VSS_25 GPP_CLK3P PCIE_RCLKN NB _LNK_CLKN PCIE_RCLKP NB _LNK_CLKP N VDD_6 VSS_31 PCIE_CK_VSS_8 CPU_HT_CLKP PCIE_VDDR_1 PCIE_VDDR_2 PCIE_VDDR_3 PCIE_VDDR_4 GPP_CLK3N PCIE_CK_VSS_9 PCIE_PVDD PCIE_PVSS P...

Page 33: ...the CPU to return to C0 or S0 state De assertion takes place following a wake up event a in S1 at an interval programmed by an SB register after de assertion of CPU_STP b in S2 after SLP_S2 is de asse...

Page 34: ...5 CBE 3 0 I O 3 3 V 5 V Tolerance Command Byte Enable 3 0 CLKRUN I O 3 3 V 5 V Tolerance Clock running is de asserted by the clock provider to indicate the system is about to shut down the PCI clock W...

Page 35: ...Positive I O See Note 1 USB_HSD 11 0 N I O AVDD_TX USB 2 0 Port 11 0 Negative I O See Note 1 USB_FSD 13 12 P I O S5_3 3V USB 1 1 port 13 12 full low speed Positive I O See Note 2 USB_FSD 13 12 N I O S...

Page 36: ...IDE_RST FC_RST IMC_GPO3 O S5_3 3V 5 V Tolerance IDE reset IMC GPIO3 7 7 Serial ATA Interface Pin Name Type Voltage Functional Description SATA_ACT GPIO67 OD 3 3 V SATA Channel Active GPIO 67 SATA_CAL...

Page 37: ...RTCCLK I O S5_3 3V VBAT 32 kHz output for internal RTC VBAT I S5_3 3V VBAT RTC battery supply X1 I S5_3 3V VBAT RTC crystal oscillator input 1 X2 O S5_3 3V VBAT RTC crystal oscillator input 2 7 10 Har...

Page 38: ...urst read and fast read cycles are not supported Pin Name Type Voltage Functional Description SPI_DI GPIO12 I O S5_3 3V SPI Data In GPIO 12 SPI_DO GPIO11 I O S5_3 3V SPI Data Output GPIO 11 SPI_CLK GP...

Page 39: ...ane control Assertion of SLP_S5 shuts power off to non critical components when system transitions to S4 or S5 state Assertion takes place sometime after CPU_STP is asserted De assertion of SLP_S5 tur...

Page 40: ...evice may transition momentarily to the active state when the device is installed but has not been initialized to drive the signal in an inactive state SLP_S2 GPM9 I O S5_3 3V S2 Sleep control Asserti...

Page 41: ...7 14 External Event General Event General Power Management General Purpose Open Collector The EXTEVENT GEVENT GPM GPOC pins of the SP5100 are multiplexed with other functions For information on how to...

Page 42: ...A20IN GEVENT0 I O 3 3V_S0 5 V Tolerance 8 2 k PU 8 2 k PD Input A20 Gate Input General Event 0 KBRST GEVENT1 I O 3 3V_S0 5 V Tolerance 8 2 k PU 8 2 k PD Input Keyboard Reset General Event 1 SMBALERT T...

Page 43: ...quest 0 Serial ATA Interlock 3 GPIO 0 SPKR GPIO2 I O 3 3V_S0 5 V Tolerance 8 2 k PU 8 2 k PD Input Speaker GPIO 2 FANOUT0 GPIO3 I O 3 3V_S0 5 V Tolerance 8 2 k PU 8 2 k PD Input Fan Output 0 GPIO 3 SM...

Page 44: ...IO 39 CLK_REQ2 SATA_IS5 FANIN3 GPIO40 I O 3 3V_S0 5 V Tolerance 8 2 k PU 8 2 k PD Input Clock Request 2 Serial ATA Interlock 5 Fan Input 3 GPIO 40 PCICLK5 GPIO41 Revision A11 PCICLK5 GPIO41 I O 3 3V_S...

Page 45: ...nput Temperature Input 1 GPIO 62 TEMPIN2 GPIO63 I O 3 3V_S5 10 k PU 10 k PD Input Temperature Input 2 GPIO 63 TEMPIN3 TALERT GPIO64 I O 3 3V_S5 10 k PU 10 k PD Input Temperature Input 3 Temperature Al...

Page 46: ...d Microcontroller IMC GPIO 14 IMC_PWM1 IMC_GPIO15 I O 3 3V_S5 10 k PU 10 k PD Input Integrated Microcontroller IMC PWM 1 IMC GPIO 15 IMC_PWM2 IMC_GPO16 I O 3 3V_S5 5 V tolerance 10 k PU 10 k PD Input...

Page 47: ...O12 I O S5_3 3V 5 V Tolerance SMBus Data 2 IMC GPIO 12 SCL3_LV IMC_GPIO13 I O 0 8 V threshold S5_3 3V domain IMC GPIO 13 SMBus Clk 3 for CPU temp status SDA3_LV IMC_GPIO14 I O 0 8 V threshold S5_3 3V...

Page 48: ...CKVDD_1 2 Reserved See SP5100 Schematic Review Checklist for how to connect SLT_GFX_CLKP O CKVDD_1 2 Reserved See SP5100 Schematic Review Checklist for how to connect SLT_GFX_CLKN O CKVDD_1 2 Reserved...

Page 49: ...PCIE_CK_VSS 1 2 V power for PCI Express and clock buffers PCIE_PVDD 1 2 V S0 S2 PCIE_VSS 1 A Link Express II PLL Power PCIE_VDDR 7 1 1 2 V S0 S2 PCIE_VSS 1 A Link Express II Analog power AVDD_SATA 7...

Page 50: ...reference Note Description AVSS_SATA 20 1 GND SATA Analog Ground Plane AVSS GND Analog Ground for Hardware Monitor AVSSC GND Analog Ground for USB PHY PLL AVSS_USB_ 24 1 GND_USB Analog Ground for USB...

Page 51: ...OHCI0 Device 18 12h Function 0 Device ID 4397h Vendor ID 1002h EHCI Device 18 12h Function 2 Device ID 4396h Vendor ID 1002h OHCI1 Device 18 12h Function 1 Device ID 4398h Vendor ID 1002h OHCI ARBITOR...

Page 52: ...EHCI bus master capabilities disabled All USB ports in suspended state D3hot Required Supported in SP5100 Deep USB Sleep state with EHCI bus master capabilities disabled All USB ports in suspended sta...

Page 53: ...21 in the case of IOAPIC Table 8 3 Causes of SMI and SCI Cause SCI SMI Additional Enable Where reported SMI Command port Yes Yes PM x0E bit 2 PM x0F bit 2 SERR port Yes Yes PCI config x64 bit 16 PCI c...

Page 54: ...include Super I O floppy disk controller keyboard controller BIOS audio TPM and system management controller BIOS ROM can also be populated on the SPI interface SP5100 can support FWH LPC or SPI type...

Page 55: ...P 2 Host IORead to LPC range I O write 1 Host Host 2 P IOWrit to LPC range DMA read 1 2 4 Peripheral Host 2 P DMA Cntrl Setup DMA data fetch DMA write 1 2 4 Peripheral P 2 Host DMA Cntrl Setup DMA da...

Page 56: ...t the IMC GPIO pins can be used as general purpose GPIOs without IMC support If not used pins on this interface should be terminated in the manner described in the SP5100 Schematic Review Checklist 8...

Page 57: ...of the data can only be performed at the software level 256 Bytes RAM 29 bit Ripple Counter 15 bit Ripple Counter 1Hz 32 768KHz Analog Portion Decode and Interface Registers Frequency Divider Alarm R...

Page 58: ...amming interface of channel 4 and 5 are under the PATA controller 3 All six channels are configured as SATA AHCI mode 512 Byte Reception FIFO 512 Byte Transmission FIFO 64 bit PCI B Link Interface dat...

Page 59: ...ls and operations of these two standards are not compatible which means AC 97 and HD Audio codecs cannot be mixed on the same link 8 9 1 HD Audio Codec Connections Figure 8 6 below shows the HD Audio...

Page 60: ...aintain state Undefined GPIO 11 12 14 31 32 46 47 53 64 66 Maintain state Undefined Notes All GPIO and GPM pins are software configurable to assume alternate functions Please refer to the GPIO section...

Page 61: ...54 VIN2 GPIO55 I O 3 3V Voltage Monitor Input 2 GPIO 55 VIN3 GPIO56 I O 3 3V Voltage Monitor Input 3 GPIO 56 VIN4 GPIO57 I O 3 3V Voltage Monitor Input 4 GPIO 57 VIN5 GPIO58 I O 3 3V Voltage Monitor I...

Page 62: ...48MHz 48MHz OSC 48MHZ from main clock generator USB Controllers and HD Audio Reference clock Table 9 2 SP5100 System Clock Input Frequency Specifications Clock Frequency Min Max USBCLK 48 000 MHz 47...

Page 63: ...ng Labels for AC Specifications of the SP5100 Diff Clocks TRISE TFALL PCIE_CLKP PCIE_CLKN VIH VIL TRISE TFALL Figure 9 3 SP5100 Diff Clocks Rise and Fall Time Measurement Table 9 4 48MHz USB Clock AC...

Page 64: ...s T65 Clock low period 13 17 s Duty Cycle 45 55 Frequency Tolerance 20 20 PPM Notes 1 Min Max specifications depend on accuracy of the crystal used 2 VIL 0 25 V VILmax 250 mV and VILmin 0 V VIH 0 75...

Page 65: ...ck low period 3 7 ns ViH Diff Clock input high 150 mV See Figure 9 3 ViL Diff Clock input low 150 mV Vcross Absolute crossing point 250 550 mV Vcross delta Variation across Vcross 140 mV Note Signal m...

Page 66: ...Power 3 3 V 3 3 V 3 3 V 3 3 0 V AVDDTX_ 5 0 AVDDRX_ 5 0 USB_AVDD 3 3 V 3 3 V 3 3 V 3 3 0 V USB_PHY_1 2V USB Phy digital power 1 2 V 1 2 V 1 2 V 1 2 0 V AVDD_SATA SATA Power 1 2 V 1 2 V 0 V 0 V PLLVDD...

Page 67: ...5 to 3 66 AVSSCK 3 3 V power for analog PLLs AVDDCK_1 2V 0 5 to 1 32 AVSSCK 1 2 V power for analog PLLs PCIE_PVDD 0 5 to 1 32 PCIE_VSS A Link Express II PLL Power PCIE_VDDR 13 1 0 5 to 1 32 PCIE_VSS...

Page 68: ...DDC Analog power for USB PHY PLL 3 135 3 3 3 465 V AVDDRX_ 5 0 Analog power for USB PHY 3 135 3 3 3 465 V AVDDTX_ 5 0 Analog power for USB PHY 3 135 3 3 3 465 V S5_3 3v 6 1 Core standby power 3 135 3...

Page 69: ...t Capacitance 10 pf All signals from SP5100 to CPU are open drain NB ALLOW_LDTSTP VIL Input Low Voltage 0 5 0 6 V VIH Input High Voltage 1 0 V VOL Output Low Voltage 0 4 V IOL 4 0 mA VOH Output High V...

Page 70: ...25 ROM_RST GPIO14 3 3 V 5 V Tolerance 0 5 0 3 VDDQ 0 7 VDDQ V5_Ref 0 25 IDE_D 15 0 GPIO 30 15 3 3 V 5 V Tolerance 0 5 0 3 VDDQ 0 7 VDDQ V5_Ref 0 25 SPI_HOLD GPIO31 S5_3 3V 0 5 0 3 S5_3 3V 0 7 S5_3 3V...

Page 71: ...5 V Tolerance 0 5 0 3 VDDQ 0 7 VDDQ V5_Ref 0 25 USB_OC 5 0 GPM 5 0 S5_3 3V 0 5 0 3 S5_3 3V 0 7 S5_3 3V S5_3 3V 0 25 BLINK GPM6 S5_3 3V 0 5 0 3 S5_3 3V 0 7 S5_3 3V S5_3 3V 0 25 SYS_RESET GPM7 S5_3 3V...

Page 72: ...0 3 S5_3 3V 0 7 S5_3 3V V5_Ref 0 25 IMC_GPIO 41 18 15 13 10 8 2 S5_3 3V 0 5 0 3 S5_3 3V 0 7 S5_3 3V S5_3 3V 0 25 Table 11 5 GPIO GEVENT Output DC Characteristics Pin Name Parameter VOL VOH Minimum Max...

Page 73: ...of 32 ms as it first goes through the internal debouncing circuit KBRST Must be asserted for 30 ns minimum The KBRST should be de asserted before A_RST and LDT_RST are de asserted 11 5 RTC Battery Cur...

Page 74: ...ble 12 1 SP5100 21 mm x 21 mm 0 8 mm Pitch 528 FCBGA Physical Dimensions Ref Min mm Nominal mm Max mm c 0 56 0 66 0 76 A 1 77 1 92 2 07 A1 0 30 0 40 0 50 A2 0 81 0 86 0 91 b 0 40 0 50 0 60 D1 20 85 21...

Page 75: ...nt device and achieve the lowest thermal contact resistance with a temperature drop across the thermal interface material of no more than 3 C Also the surface flatness of the metal spreader should be...

Page 76: ...e rated junction temperature is the junction temperature at which the device can operate without causing damage to the ASIC 3 The ambient temperature is defined as the temperature of the local intake...

Page 77: ...ion to resetting the test controller asynchronously with TEST1 a bit sequence can also be used to synchronously change the test mode Table 14 3 shows the legal bit sequences for TEST0 Note Once the Te...

Page 78: ...ure below XOR Start Signal G F E D C B A Figure 14 2 A Generic XOR Chain Pin A is assigned to the output direction and pins B through F are assigned to the input direction It can be seen that after al...

Page 79: ...figured as an output KBRST GEVENT1 is the start of the chain and SERIRQ is the end of the chain Table 14 5 lists all pads that are on the SP5100 XOR chain as well as and their order of connection Pads...

Page 80: ...6 FANOUT0 GPIO3 77 FANOUT2 GPIO49 78 FANOUT1 GPIO48 79 AZ_SDOUT 80 AZ_BITCLK 81 AZ_SYNC 82 A_RST 83 AZ_SDIN3 GPIO46 84 PCIRST 85 AZ_RST 86 AZ_SDIN2 GPIO44 87 AZ_DOCK_RST GPM8 88 LPC_PME GEVENT3 89 SUS...

Page 81: ...2 154 IMC_GPIO33 155 IMC_GPIO0 156 LDT_PG 157 IMC_GPIO1 158 IMC_GPIO4 159 IMC_GPIO29 160 IMC_GPIO31 161 IMC_GPIO30 162 IMC_GPIO7 163 IMC_GPIO25 164 IMC_GPIO27 XOR Pin Name 165 IMC_GPIO28 166 IMC_GPIO2...

Page 82: ...E_D2 GPIO17 214 IDE_D13 GPIO28 215 IDE_D11 GPIO26 216 IDE_D4 GPIO19 217 IDE_D9 GPIO24 218 IDE_D6 GPIO21 219 IDE_D5 GPIO20 220 IDE_D10 GPIO25 221 IDE_D8 GPIO23 XOR Pin Name 222 IDE_D7 GPIO22 223 SATA_I...

Page 83: ...can be left floating during an XOR test That includes the output of the XOR chain FANOUT0 GPIO3 and other pads shown in Table 14 6 below Table 14 6 Pins Excluded from the XOR Chain Pin Name Descripti...

Page 84: ...CIE_TX2P U25 PCIE_TX2N U24 PCIE_TX3P T23 PCIE_TX3N T22 PCIE_RX0P U22 PCIE_RX0N U21 PCIE_RX1P U19 PCIE_RX1N V19 PCIE_RX2P R20 PCIE_RX2N R21 PCIE_RX3P R18 PCIE_RX3N R17 PCIE_CALRP T25 PCIE_CALRN T24 PCI...

Page 85: ...HSD3N G14 USB_HSD2P H14 USB_HSD2N H15 USB_HSD1P A13 USB_HSD1N B13 USB_HSD0P B14 USB_HSD0N A14 USBCLK 14M_25M_48M_OSC C8 USB_RCOMP G8 ATA66 100 133 IDE_RST F_RST IMC_GPO3 F25 IDE_IORDY AA24 IDE_IRQ AA2...

Page 86: ...Clocks 14M_X1 J21 14M_X2 J20 USBCLK 14M_25M_48M_OSC C8 25M_48M_66M_OSC L18 PCIE_RCLKP NB_LNK_CLKP N25 PCIE_RCLKN NB_LNK_CLKN N24 NB_DISP_CLKP K23 NB_DISP_CLKN K22 NB_HT_CLKP M24 NB_HT_CLKN M25 CPU_HT_...

Page 87: ...IO27 B23 IMC_GPIO28 A23 IMC_GPIO29 C22 IMC_GPIO30 A22 IMC_GPIO31 B22 IMC_GPIO32 B21 IMC_GPIO33 A21 IMC_GPIO34 D20 IMC_GPIO35 C20 IMC_GPIO36 A20 IMC_GPIO37 B20 IMC_GPIO38 B19 IMC_GPIO39 A19 IMC_GPIO40...

Page 88: ...Q1 SATA_IS4 FANOUT3 GPIO39 V17 CLK_REQ2 SATA_IS5 FANIN3 GPIO40 W20 PCICLK5 GPIO41 T3 AZ_SDIN0 GPIO42 J7 AZ_SDIN1 GPIO43 J8 AZ_SDIN2 GPIO44 L8 AZ_SDIN3 GPIO46 M3 SPI_CLK GPIO47 D1 FANOUT1 GPIO48 M5 FAN...

Page 89: ...g Grounds PCIE_CK_VSS_1 H18 PCIE_CK_VSS_10 R16 PCIE_CK_VSS_11 R19 PCIE_CK_VSS_12 T17 PCIE_CK_VSS_13 U18 PCIE_CK_VSS_14 U20 PCIE_CK_VSS_15 V18 PCIE_CK_VSS_16 V20 PCIE_CK_VSS_17 V21 PCIE_CK_VSS_18 W19 P...

Page 90: ...S5_3 3V_5 J5 S5_3 3V_6 L1 S5_3 3V_7 L2 1 2V Standby Power S5_1 2V_1 G2 S5_1 2V_2 G4 USB Phy Digital Power USB_PHY_1 2V_1 A10 USB_PHY_1 2V_2 B10 Digital Ground VSS_1 A2 VSS_2 A25 VSS_3 B1 VSS_4 D7 VSS_...

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