AMD SP5100 Databook
44409 Rev. 1.70 October 10
34
Signal Description
Note:
LPCCLK[1:0] can be assigned to any LPC device. LPCCLK0 will be active during S2 – S5 states if the IMC is
enabled. LPCCLK1 will be disabled in S2 to S5 states. PCI Clock can be used for additional LPC devices that do not
require clock in S2 –S5 states.
7.3
A-Link Express II Interface
Pin Name
Type
Voltage
Functional Description
PCIE_TX[3:0]P
O
1.2 V (Filtered)
A-Link Express II Lane 3-0 Transmit Positive
PCIE_TX[3:0]N
O
A-Link Express II Lane 3-0 Transmit Negative
PCIE_RX[3:0]P
I
A-Link Express II Lane 3-0 Receive Positive
PCIE_RX[3:0]N
I
A-Link Express II Lane 3-0 Receive Negative
PCIE_RCLKP
I/O
A-Link Express II Reference Clock Positive
PCIE_RCLKN
I/O
A-Link Express II Reference Clock Negative
PCIE_CALRP
O
A-Link Express II Calibration, TX termination reference
resistor connection
PCIE_CALRN
O
A-Link Express II Calibration, RX termination reference
resistor connection
7.4
PCI Interface (PCI Host Bus and Internal PCI/PCI Bridge)
Pin Name
Type
Voltage
Functional Description
AD[31:0]
I/O
3.3 V (5-V Tolerance) PCI Bus Address/Data [31:0]
BMREQ#/REQ5#/
GPIO65
I/O
3.3 V (5-V Tolerance) Bus master REQ# / PCI Request 5 Input / GPIO 65
CBE[3:0]#
I/O
3.3 V (5-V Tolerance) Command/Byte Enable[3:0]
CLKRUN#
I/O
3.3 V (5-V Tolerance)
Clock running is de-asserted by the clock provider to
indicate the system is about to shut down the PCI clock.
When it is driven low by other agents, it means the agent
is requesting the clock provider not to deactivate the clock.
DEVSEL#
I/O
3.3 V (5-V Tolerance)
Device Select
Device Select: driven by target to indicate it has decoded
its address as the target of the current access.
FRAME#
I/O
3.3 V (5-V Tolerance)
Cycle Frame: driven by the current master to indicate the
beginning and duration of an access.
GNT#[2:0]
O
3.3 V (5-V Tolerance)
PCI Bus Grant [2:0] from the SP5100: indicates to the
agent that access to the bus has been granted.
GNT3#/GPIO72
O
3.3 V (5-V Tolerance) PCI Bus Grant 3 from SP5100 / GPIO 72
GNT4#/GPIO73
I/O
3.3 V (5-V Tolerance) PCI Bus Grant 4 from SP5100 / GPIO 73
INT[H:E]#/GPIO[36:33]
I/O
3.3 V (5-V Tolerance) PCI Interrupt [H:E] / GPIO [36:33]
IRDY#
I/O
3.3 V (5-V Tolerance)
Initiator Ready: indicates the initiating agent’s ability to
complete the current data phase of the transaction
LDRQ1#/GNT5#/
GPIO68
I/O
3.3 V (5-V Tolerance)
Encoded DMA/Bus Master Request 1 / PCI bus Grant 5
from SP5100 /GPIO 68
LOCK#
I/OD
3.3 V (5-V Tolerance) PCI Bus Lock
PAR
I/O
3.3 V (5-V Tolerance) PCI Bus Parity
PCICLK[4:0]
O
3.3 V (5-V Tolerance) 33-MHz PCI clocks [4:0]
PCICLK5/GPIO41
O
3.3 V (5-V Tolerance) 33-MHz PCI clock 5 / LPC CLK 0