AMD SP5100, Data Book, Page: 22 / 90

AMD SP5100 Databook 44409 Rev. 1.70 October 10
22
SP5100 Strap Information
Pad Name Strap Name Type Description
LPCCLK0
IMC_ENABLE I
Integrated Microcontroller (IMC)
0 V – Disable IMC
3.3 V – Enable IMC
PCI_ROM_BOOT II
Revision A11 strap defination
Booting from PCI memory
0 V – disable PCI ROM boot ( Default )
3.3 V – enable PCI ROM boot
Note: This feature is for debug pupose only. After a G3
→
S5 transition the system will allow boot from PCI memory
only once. Subsequent S5
→
S0 transition will not boot
from PCI memory.
LPCCLK1
PCIE_PLL_ENAB
LE
II
Enable PCI Expresse
®
PLL
0 V – Normal operation. PCI Express clock enabled for
internal PLL reference clock.
3.3 V – Test / debug. PCI Express clock disconnected
from internal PLL.
AZ_RST#
IMC_ENABLE I
Revision A11 strap defination
Integrated Microcontroller (IMC)
0 V – disable IMC
3.3 V – enable IMC
PCI_ROM_BOOT II
Booting from PCI memory
0 V – disable PCI ROM boot ( Default )
3.3 V – enable PCI ROM boot
Note: This feature is for debug pupose only. After a G3
→
S5 transition the system will allow boot from PCI memory
only once. Subsequent S5
→
S0 transition will not boot
from PCI memory.
PCICLK5 Reserved — Reserved
PCICLK4 Reserved — Reserved
PCICLK3
Debug_Straps II
Enable/Disable additional straps for debugging (see
Table 4-2
)
0 V – use hardcoded defaults for Debug
Straps (Default)
3.3 V – enable additional Debug Straps
PCICLK2 Watchdog_Enable II
Watchdog function
0 V – disable watchdog function on NB_PWRGD ball
3.3 V – enable watchdog function on NB_PWRGD ball
Table 4-2: Debug Straps
Pad Name Strap Name Type Description
PCI_AD30 Reserved — Reserved (Internal PU of 15 k
Ω
)
PCI_AD29 Reserved — Reserved (Internal PU of 15 k
Ω
)
PCI_AD28 Reset_Length II
Generate a short reset
0 V – Use short reset (reserved, do not use)
3.3 V – Use long reset (
Default )
(Internal PU of 15 k
Ω
)