AMD SP5100 Databook
44409 Rev. 1.70 October 10
78
Testability
active. Note that once TEST1 is set to one, TEST0 needs to be asserted to one for at least 8 clocks
before transmitting the test mode bit sequence. The rising of “Internal Test Mode” in the diagram indicates
the time when the SP5100 enters into test mode.
TEST0
TEST1
Osc
( TEST0 = 1 ) >
8 Osc clocks
Bit 4
Bit 1
Bit 2
Bit 3
Bit 0
Internal Test Mode
Figure 14-1: Test Mode Capturing Sequence Timing
14.2 XOR Chain Test Mode
14.2.1 Brief Description of an XOR Chain
A sample of a generic XOR chain is shown in the figure below.
XOR Start Signal
G
F
E
D
C
B
A
Figure 14-2: A Generic XOR Chain
Pin A is assigned to the output direction, and pins B through F are assigned to the input direction.
It can be seen that after all pins from B to F are assigned to logic 0 or 1, a logic change in any
one of these pins will toggle the output pin A.
The following is the truth table for the XOR Chain shown in Figure 14-2
The XOR start signal is
assumed to be logic 1.This is an internal signal to the ASIC and is not part of the XOR tree pins
listed in Table 14-5
Once the inputs are set to the respective value the output pin will reflect the correct value within
200 ns. Note: OSC clock is not required to be running after the mode is already set and the pads
are exercised in XOR Tree function.