AMD SP5100, Data Book, Page: 77 / 90

44409 Rev. 1.70 October 10 AMD SP5100 Databook
Testability
77
14 Testability
14.1 Test Control Signals
Table 14-1 below shows the signals used for the integrated test controller of the SP5100.
Table 14-1: Signals for the Test Controller of the SP5100
Signal Name Description
14M_X1 / 14M_X2 25-MHz Reference Clock.
TEST0 Test0 input.
TEST1 Test1 input.
TEST2 Test2 input.
Table 14-2 shows how Test[2:0] are used to select the normal operation, ASIC debug, or test mode.
Table 14-2: Test Mode Signals
TEST2 TEST1 TEST0 Test Mode Description
0 0 0 None Normal operation
0 0 1 Reserved Reserved for ASIC debug
0 1 x Test Mode EnableTest Mode
1 X X Reserved Reserved for ASIC debug
When TEST2 is low, a low on TEST1 will reset all test logic and allow TEST0 to choose between normal
operation and the reserved debug mode. A high on TEST1 should be followed by a bit sequence on
TEST0 to define the test mode into which the SP5100 will enter. A new test mode can be entered when a
new bit sequence is transmitted. In addition to resetting the test controller asynchronously with TEST1, a
bit sequence can also be used to synchronously change the test mode. Table 14-3
shows the legal bit
sequences for TEST0. Note: Once the Test mode or Test mode and sub test mode is entered, Test2 and
Test1 should be kept at 0, 1 respectively until the requirement for the Test Mode is completed.
Table 14-3: TEST0 Bit Sequence
TEST0 bit sequence Test Mode
11111 Look for first 0 to define a new test mode
00000 Reserved
00001 Alt Pull High Test
00010 Pull Outputs High
00011 Pull Outputs Low
00100 Pull Outputs to Z
00101 XOR Test Mode
Figure 14-1 illustrates the data timing for the test signals with respect to the OSC clock. Any timing
reference referred in this section is assumed to be based on OSC clock running at 25 MHz. The OSC
clock can be slowed down to 1 MHz as long as the bit stream applied on TEST0 pin is also in sync with
this clock. The 25-MHz OSC clock should be disconnected first. For setting any Test 0 bit sequence, the
OSC clock is required only up-to the time the mode set is completed. After this the clock can be stopped
and as long as TEST1 and Test2 pins are set to {1, 0} respectively to maintain the selected mode to be