44409
Rev.
1.70
October 10
AMD SP5100 Databook
Signal Description
39
Pin Name
Type
Voltage
Functional Description
PWR_GOOD
I
S5_3.3V
SB power good input
Assertion of PWR_GOOD by the SB power good circuit on the
motherboard indicates that power supplies to the SB are valid.
Assertion takes place sometime after NB Power Good is asserted.
De-assertion of PWR_GOOD by the SB power good circuit indicates
that the power supplies to the SB are NOT valid. De-assertion takes
place sometime after SLP_S3# or SLP_S5#’s assertion, or after
Power Supply Power Good is de-asserted.
RI#/EXTEVNT0#
I/O
S5_3.3V
Ring Indicator / External Event 0
SMARTVOLT2/
SHUTDOWN#/
GPIO5
I/O
S0
Set system rails to lower voltage / System Shutdown / GPIO5
System Shutdown:
Assertion will cause the SP5100 to assert
SLP_S3# and SLP_S5# to force system to transition to S5
immediately, without waiting for the STPGNT message from
the processor.
SLP_S3#
O
S5_3.3V
S3 Sleep Power plane control
Assertion of SLP_S3# shuts off power to non-critical components
when system transitions to S3, S4, or S5 states. Assertion takes
place sometime after CPU_STP# is asserted.
De-assertion of SLP_S3# turns on power to non-critical components
when system transitions from S3, S4, or S5 back to S0. De-
assertion takes place sometime after a wake-up event has been
triggered.
SLP_S5#
O
S5_3.3V
S5 Sleep Power plane control -
Assertion of SLP_S5# shuts power off to non-critical components
when system transitions to S4 or S5 state. Assertion takes place
sometime after CPU_STP# is asserted.
De-assertion of SLP_S5# turns on power to non-critical components
when transitioning from S4/S5 back to S0 state. De-assertion takes
place sometime after a wake-up event is triggered.
SMBALERT#/
THRMTRIP#/
GEVENT2#
I/O
S5_3.3V
SMBus Alert / Thermal Trip / General Event 2
Thermal Trip: Signal indicates to the SP5100 that a thermal trip has
occurred. Its assertion will cause the SP5100 to transition the
system to S5 immediately, without waiting for the STPGNT
message from the processor.
SUS_STAT#
OD
S5_3.3V
Suspend Status -
Assertion by the SP5100 indicates that the system will be entering a
low-power state soon. The signal is monitored by those devices with
memory that needs to switch from normal refresh to suspend
refresh mode when the system transitions to a low-power state.
Assertion takes place after the Stop Grant message from the CPU is
received by the system.
De-assertion by the SP5100 indicates that the system is exiting a
low power state now and is returning to S0
. De-assertion
takes
place after LDT_STP# is de
-
asserted.
TEMPIN3/
TALERT#/
GPIO64
I/O
S5_3.3V
Temperature Monitor Input 3/ Thermal Alert / GPIO 64
Thermal Alert: The signal is a thermal alert to the SP5100. SP5100
can be programmed to generate an SMI#, SCI, or IRQ13 through
GPE, or generate an SMI# without GPE in response to the signal’s
assertion. See the
AMD SP5100 Register Reference Guide
for
details.