AMD SP5100 Databook
44409 Rev. 1.70 October 10
66
States of Power Rails during ACPI S1 to S5 States
10 States of Power Rails during ACPI S1 to S5 States
SP5100 supports the ACPI states S1 to S5. Table 10-1
below shows the expected state of each power
rail during these power states.
Table 10-1: State of Each Power Rail during ACPI S1 to S5 States
Pin name
Schematic
Signal
ACPI STATE
S0
S1/S2
S3
S4/S5
VDDQ
+3.3_SB_R
+3.3 V
+3.3 V
0 V
0 V
VDD
+1.2_SB_R
+1.2 V
+1.2 V
0 V
0 V
S5_1.2V
S5 Power
+1.2 V
+1.2 V
+1.2 V
+1.2 V
VDD33_18
VDD33_18
3.3V
3.3V
0 V
0 V
AVDDC
Analog USB
2.0 Power
+3.3 V
+3.3 V
+3.3 V
+3.3 / 0 V
AVDDTX_[5:0]
/AVDDRX_[5:0]
USB_AVDD
+3.3 V
+3.3 V
+3.3 V
+3.3 / 0 V
USB_PHY_1.2V
USB Phy
digital power
+1.2 V
+1.2 V
+1.2 V
+1.2 / 0 V
AVDD_SATA
SATA Power
+1.2 V
+1.2 V
0 V
0 V
PLLVDD_SATA
SATA PLL
Power
+1.2 V
+1.2 V
0 V
0 V
XTLVDD_SATA
SATA XTAL
Power
+3.3 V
+3.3 V
0 V
0 V
V5_VREF
+5-V Ref
Voltage
+5.0 V
+5.0 V
0 V
0 V
AVDDCK_3.3V
PLL Analog
Power
+3.3 V
+3.3 V
0 V
0 V
AVDDCK_1.2V
PLL Digital
Power
+1.2 V
+1.2 V
0 V
0 V
S5_3.3V
S5 I/O
Power
+3.3 V
+3.3 V
+3.3 V
+3.3 V
PCIE_PVDD
PCI
Express
®
PLL Power
+1.2 V
+1.2 V
0 V
0 V
PCIE_VDDR
PCI Express
I/O Power
+1.2 V
+1.2 V
0 V
0 V
SLP_S3#
SLP_S3#
+3.3 V
+3.3 V
0 V
0 V
SLP_S5#
SLP_S5#
+3.3 V
+3.3 V
+3.3 V
0 V
PWR_GOOD
SB_PWROK
+3.3 V
+3.3 V
0 V
0 V
SUS_STAT#
SUS_STAT#
+3.3 V
0 V
0 V
0 V
RSMRST#
RSMRST#
+3.3 V
+3.3 V
+3.3 V
+3.3 V