AMD SP5100 Databook
44409 Rev. 1.70 October 10
42
Signal Description
Ball Name
(
Default Function
in Blue
)
Type
Voltage and
Domain
Internal
Resistor
(
Default in
Blue
)
Default
Type
(
Default
State in
Blue
)
Functional Description
USB_OC3#/
IR_RX1/
GPM3#
I/O
3.3V_S5
10-k
Ω
PU
10-k
Ω PD
Input
USB Over Current 3/
Infrared Receive 1/
GPM 3
USB_OC4#/
IR_RX0/
GPM4#
I/O
3.3V_S5
10-k
Ω PU
10-k
Ω PD
Input
USB Over Current 4/ Infrared
Receive 0/
GPM 4
USB_OC5#/
IR_TX0/
GPM5#
I/O/
OD
3.3V_S5
10-k
Ω PU
10-k
Ω PD
Input
USB Over Current 5/
Infrared Transmit 0/
GPM 5
BLINK/
GPM6#
I/O
3.3V_S5
10-k
Ω PU
10-k
Ω PD
Input
LED Blink/
GPM 6
SYS_RESET#/
GPM7#
I/O
3.3V_S5
10-k
Ω PU
10-k
Ω PD
Input
System Reset/
GPM 7
AZ_DOCK_RST/
GPM8#
I/O
3.3V_S5
10-k
Ω PU
10-k
Ω PD
Input
HD Audio Dock Reset/
GPM 8
SLP_S2/
GPM9#
I/O
3.3V_S5
10-k
Ω PU
10-k
Ω PD
Input
Sleep S2/
GPM 9
RI#/
EXTEVENT0#
I/O
3.3V_S5
10-k
Ω PU
10-k
Ω PD
Input
Ring Indicator/
External Event 0
LPC_SMI#/
EXTEVENT1#
I/O
3.3V_S0
(5-V Tolerance)
8.2-k
Ω PU
8.2-k
Ω PD
Input
LPC System Management
Interrupt / External Event 1
GA20IN/
GEVENT0#
I/O
3.3V_S0
(5-V Tolerance)
8.2-k
Ω PU
8.2-k
Ω PD
Input
A20 Gate Input/
General Event 0
KBRST#/
GEVENT1#
I/O
3.3V_S0
(5-V Tolerance)
8.2-k
Ω PU
8.2-k
Ω PD
Input
Keyboard Reset/
General Event 1
SMBALERT#/
THRMTRIP#
/
GEVENT2#
I/O
3.3V_S5
10-k
Ω PU
10-k
Ω PD
Input
SM Bus Alert/
Thermal Trip/
General Event 2
LPC_PME#/
GEVENT3#
I/O
3.3V_S5
10-k
Ω PU
10-k
Ω PD
Input
LPC Power Management
Event / General Event 3
PCI_PME#/
GEVENT4#
I/O
3.3V_S5
10-k
Ω PU
10-k
Ω PD
Input
PCI Power Management
Event / General Event 4
S3_STATE/
GEVENT5#
I/O
3.3V_S5
10-k
Ω PU
10-k
Ω PD
Output
Low
S3 State/
General Event 5
USB_OC6#/
IR_TX1/
GEVENT6#
I/O
3.3V_S5
10-k
Ω PU
10-k
Ω PD
Input
USB Over Current 6/
Infrared Transmit 1/
General Event 6
DDR3_RST#/
GEVENT7#
I/O
3.3V_S5
10-k
Ω PU
10-k
Ω PD
Input
DDR3 Memory Reset/
General Event 7
WAKE#/
GEVENT8#
I/O
3.3V_S5
10-k
Ω PU
10-k
Ω PD
Input
PCI Express
®
Wake/
General Event 8
SCL0/
GPOC0#
I/O
3.3V_S0
(5-V Tolerance)
8.2-k
Ω PU
8.2-k
Ω PD
Input
SMBus Clock 0/
GP Open Collector 0
SDA0/
GPOC1#
I/O
3.3V_S0
(5-V Tolerance)
8.2-k
Ω PU
8.2-k
Ω PD
Input
SMBus Data 0/
GP Open Collector 1
SCL1/
GPOC2#
I/O
3.3V_S5
10-k
Ω PU
10-k
Ω PD
Input
SMBus Clock 1/
GP Open Collector 2
SDA1/
GPOC3#
I/O
3.3V_S5
10-k
Ω PU
10-k
Ω PD
Input
SMBus Data 1/
GP Open Collector 3