AMD SP5100 Databook
44409 Rev. 1.70 October 10
40
Signal Description
Pin Name
Type
Voltage
Functional Description
S3_STATE/
GEVENT5#
I/O
S5_3.3V
S3 State: Assertion of S3_STATE by the SP5100 indicates to the
power supply that the system has transitioned into S3 state.
Asserted after the Sleep S3 command is completed. De-assertion
indicates that the system is leaving S3 state. De-assertion takes
place after SUS_STAT# is de-asserted.
WAKE#/
GEVENT8#
I/O
S5_3.3V
PCI Express
®
Wake /General Event 8
PCI Express Wake: On Power up this pin will function as WAKE# in
legacy mode. Optionally, WAKE# in native mode can be enabled
after power up, only by software. When the pin is asserted (active
low) the Southbridge will generate the wake event. The Wake#
function is supported in S5 through S0, with the following
restriction:
Wake function in S5 state—
When transitioning from G3 to S5,
the WAKE# function will not be enabled. However, after an initial
transition from S5 to S0 and back to S5, the WAKE# function will
be enabled. It will stay enabled for any subsequent transition
from S0 to S5.
Care must be taken when plugging in PCIe devices. The system
should be transitioned into the G3 state (S5 power off) before a
PCIe device is installed. Plugging in a PCIe device when the system
is in S5 state may cause the system to wake up, because the
WAKE# signal driven by the PCIe device may transition
momentarily to the active state when the device is installed but has
not been initialized to drive the signal in an inactive state.
SLP_S2/GPM9#
I/O
S5_3.3V
S2 Sleep control: Assertion of SLP_S2 shuts off clocks when
system transitions to S2 state, and it takes place sometime after
CPU_STP# is asserted.
De-assertion of SLP_S2 turns on clocks when system transition
s
from S2 back to S0, and it takes place sometime after a wake-up
event
has been
triggered.
ALLOW_LDTSTP
I/OD
0.8-V
threshold,
S5_3.3V
domain
ALLOW_LDTSTP: It is an input from NB to allow assertion of
LDT_STP#. When ALLOW_LDTSTP is de-asserted, SP5100 cannot
assert LDT_STP#. ALLOW_LDTSTP can be used to implement
stutter mode operation for the CPU. Starting with RS78x, NB will
control the LDT_STP# during C state. In this configuration, SB can
drive ALLOW_LDTSTP to inform NB when it can assert LDT_STP#.
NB_PWRGD
OD
3.3 V
Northbridge Power good
7.13 SMBus Interface / General Purpose Open Collector
Pin Name
Type
Voltage
Functional Description
SCL0/GPOC0#
I/OD
3.3 V (5-V Tolerance)
SMBus Clock 0 / General Purpose Open Collector 0
Note:
Pin type is I/O when the pin is configured as
GPIO.
SDA0/GPOC1#
I/OD
3.3 V (5-V Tolerance)
SMBus Data 0 / General Purpose Open Collector 1
Note:
Pin type is I/O when the pin is configured as
GPIO.
SCL1/GPOC2#
I/OD
S5_3.3V
SMBus Clock 1 / General Purpose Open Collector 2
Note:
Pin type is I/O when the pin is configured as
GPIO.
SDA1/GPOC3#
I/OD
S5_3.3V
SMBus Data 1 / General Purpose Open Collector 3
Note:
Pin type is I/O when the pin is configured as
GPIO.