AMD SP5100 Databook
44409 Rev. 1.70 October 10
20
SP5100 Strap Information
4 SP5100 Strap Information
There are two kinds of strap-latching logic, Type I and Type II. Type I straps will be latched on G3 to S5
transition on rising edge of RSMRST#. Type II straps are latched on S5 to S0 transition after rising edge
of PWR_GOOD assertion.
S5_1.2V
STRAPs (board)
PwrGood
RsmRst#
VDD
Straps Type I
Straps I
Capture
Straps Type II
Straps I
Straps Type I
Straps Type II
Undefined
Straps II
Capture
Straps II
Don' t care
Figure 4-1: Straps Capture
POWER GOOD
PCI_RST#
PCI Clock signal is tristate can be
High or Low
PCI device will
functional here
PCI device in Reset
PCI reset asserted
PCI Clock stable 33 MHz
PCI Clock
Strap signal
must be stable
and at valid
state
Undefined
Timing is system
dependent
25 ms
T1
~31 ms
S5 3.3V /S5 1.2V
Figure 4-2: Type II Straps Capture timing