57
Chapter 3: Testing Performance
To test the single-clock, multiple-edge, state acquisition
To test the single-clock, multiple-edge, state acquisition
Testing the single-clock, multiple-edge, state acquisition verifies the performance
of the following specifications:
•
Minimum master-to-master clock time.
•
Maximum state acquisition speed.
•
Setup/Hold time for single-clock, multiple-edge, state acquisition.
This test checks two combinations of data using a multiple-edge single clock at
two selected setup/hold times.
Equipment Required
Set up the equipment
1
If you have not already done so, do the following procedures:
“To set up the test equipment and the logic analyzer” on page 23
“To set up the logic analyzer for the state mode tests” on page 33
2
Modify the following pulse generator settings:
Period: 10.000 ns
Channel 2: Width 3.000 ns
Channel 2: Pulse
÷
1
Channel 1: Pulse
Channel 1: Width 5.000 ns
Equipment
Critical Specifications
Recommended Model/Part
Pulse Generator
200 MHz 3.0 ns pulse width,
<
600 ps rise time
8133A option 003
Digitizing Oscilloscope
≥
6 GHz bandwidth,
<
58 ps rise time
54750A w/ 54751A
Adapter
SMA(m)-BNC(f)
1250-1200
SMA Coax Cable (Qty 3)
18 GHz bandwidth
8120-4948
Coupler
BNC(m)(m)
1250-0216
BNC Test Connector,
6x2 (Qty 4)
Summary of Contents for 1680 series
Page 13: ...13 Chapter 1 General Information Dimensions 1680A AD Series 1690A AD Series...
Page 74: ...74 Chapter 3 Testing Performance Performance Test Record...
Page 142: ...142 Chapter 6 Replacing Assemblies 1690A AD series disassembly assembly...
Page 172: ...172 Chapter 8 Theory of Operation Self Tests Descriptions...
Page 174: ......