52
Chapter 3: Testing Performance
To test the multiple-clock state acquisition
b
On the oscilloscope, select [Shift] + width: channel 1, then select
[Enter] to display the data signal pulse width (+ width (1)).
c
If the pulse width is outside the limits, adjust the pulse generator
channel 2 width until the pulse width is within limits.
Check the setup/hold with single clock edges, multiple
clocks
The following setup/hold combinations will be tested.
Setup/Hold Combinations
1
Disable the pulse generator channel 1 COMP (LED off).
2
Using the Delay mode of the pulse generator channel 1, position the pulses
according to the setup time of the setup/hold combination selected,
+0.0 ps or
−
100 ps as measured on the oscilloscope:
a
On the Oscilloscope, select [Define meas] Define
∆
Time - Stop edge:
rising, Edge number 2.
Test
Combination
Setup/Hold
Times
Setup/Hold
Window
Sample Position
(in middle of Window)
1
5.0/-2.0 ns
3.0 ns
-3.5 ns
2
-1.5/4.50 ns
3.0 ns
+3.0 ns
Summary of Contents for 1680 series
Page 13: ...13 Chapter 1 General Information Dimensions 1680A AD Series 1690A AD Series...
Page 74: ...74 Chapter 3 Testing Performance Performance Test Record...
Page 142: ...142 Chapter 6 Replacing Assemblies 1690A AD series disassembly assembly...
Page 172: ...172 Chapter 8 Theory of Operation Self Tests Descriptions...
Page 174: ......