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Chapter 3: Testing Performance
To test the single-clock, multiple-edge, state acquisition
Test the next channels (1680/81A,AD and 1690/91A,AD)
Connect the next combination of data channels and clock channels, then repeat
the previous test.
Start with “Connect and configure the logic analyzer” on page 58, connect the
next combination, then continue through the complete test.
Summary of Contents for 1680 series
Page 13: ...13 Chapter 1 General Information Dimensions 1680A AD Series 1690A AD Series...
Page 74: ...74 Chapter 3 Testing Performance Performance Test Record...
Page 142: ...142 Chapter 6 Replacing Assemblies 1690A AD series disassembly assembly...
Page 172: ...172 Chapter 8 Theory of Operation Self Tests Descriptions...
Page 174: ......