6-1
IM AQ6370C-17EN
Status Registers
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App
Index
Chapter 6
Status Registers
6.1 Status Registers
This instrument is equipped with the status registers shown in the table below. See the
next page for a diagram of all status registers.
This instrument has the following status registers defined by IEEE 488-2 and SCPI:
• Status byte registers
• Standard event registers
• Operation status registers
• Questionable status registers
Also, this instrument has an operation status bit (OPS) and a questionable status
bit (QUS), each of which contains the summary information of each piece of register
information, as the extension bits of the status byte register.
List of Status Registers
Register Name
Description
Status byte registers
Register defined by IEEE 488.2
STB: Status Byte Register
Same as the above
SRE: Service Request Enable Register Same as the above
Standard event registers
Register defined by IEEE 488.2
ESR: Standard Event Status Register Same as the above
ESE: Standard Event Status Register Same as the above
Operation status registers
Provides information on operation execution
(such as being swept, copied, or under calibration).
Operation Event Register
A register indicating the presence/absence of an
event. Event will be latched.
Operation Event Enable Register
A condition mask register used when the summary
bit (OPS) is created.
Questionable status registers
Not assigned yet.
Questionable Event Register
A register indicating the presence/absence of an
event. An event will be latched.
Questionable Event Enable Register
A condition mask register used when the summary
bit (QUS) is created.