VCU1287 Characterization Board
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28
UG1121 (v1.0) December 11, 2015
Chapter 3:
Board Component Descriptions
SuperClock-2 Module
The SuperClock-2 module (callout 11,
Figure 2-1
) connects to the clock module interface
connector (J36) and provides a programmable, low-noise and low-jitter clock source for the
VCU1287 board. The clock module maps to FPGA I/O by way of 14 control pins, 2 LVDS
pairs, 1 regional clock pair, and 1 reset pin.
Table 3-10
shows the FPGA I/O mapping for the
SuperClock-2 module interface. The VCU1287 board supplies UTIL_5V0, UTIL_3V3, UTIL_2V5
and VCCO_HP input power to the
Table 3-10
clock module interface.
Table 3-10:
SuperClock-2 FPGA I/O Mapping
FPGA(U1)
Schematic Net
Name
J36 Pin
Pin
Function
Direction
IOSTANDARD
Pin
Function
Direction
L13
Clock recovery
Input
LVDS
CM_LVDS1_P
1
Clock recovery
Output
K13
Clock recovery
Input
LVDS
CM_LVDS1_N
3
Clock recovery
Output
J33
Clock recovery
Input
LVDS
CM_LVDS2_P
9
Clock recovery
Output
H33
Clock recovery
Input
LVDS
CM_LVDS2_N
11
Clock recovery
Output
G26
Regional clock
Input
LVDS
CM_GCLK_P
25
Global clock
Output
G27
Regional clock
Input
LVDS
CM_GCLK_N
27
Global clock
Output
B30
Control I/O
Output
LVCMOS
CM_H_DEC
67
DEC
Input
A30
Control I/O
Output
LVCMOS
CM_H_INC
69
INC
Input
B29
Control I/O
Output
LVCMOS
CM_FS_ALIGN
71
ALIGN
Input
A29
Control I/O
Input
LVCMOS
CM_H_LOL
79
LOL
Output
A27
Control I/O
Output
LVCMOS
CM_H_INT_ALRM
81
INT_ALRM
Input
A28
Control I/O
Output
LVCMOS
CM_C1B
83
C1B
Input
E30
Control I/O
Output
LVCMOS
CM_C2B
85
C2B
Input
D30
Control I/O
Output
LVCMOS
CM_C3B
87
C3B
Input
D29
CONTROL I/O
Output
LVCMOS
CM_C1A
89
C1A
Input
C29
CONTROL I/O
Output
LVCMOS
CM_C2A
91
C2A
Input
C27
CONTROL I/O
Output
LVCMOS
CM_H_CS0_C3A
95
CS0_C3A
Input
B27
CONTROL I/O
Output
LVCMOS
CM_H_CS1_C4A
97
CS1_C4A
Input
C28
CM_RESET
Output
LVCMOS
CM_RST
66
RESET_B
Input
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