Xilinx Virtex UltraScale FPGA VCU1287 Скачать руководство пользователя страница 59

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VCU1287 Characterization Board

www.xilinx.com

UG1121 (v1.0) December 11, 2015

Appendix C

Master Constraints File Listing

Introduction

The VCU1287 board master Xilinx design constraints (XDC) file template provides for

designs targeting the VCU1287 UltraScale FPGA GTH and GTY Transceiver Characterization

Board. Net names in the listed constraints correlate with net names on the VCU1287 board

schematic. Identify the appropriate pins and replace the net names with net names in the

user RTL. See the

Vivado Design Suite User Guide: Using Constraints

(UG903)

[Ref 3]

for more

information.

IMPORTANT:

See the

Xilinx Virtex UltraScale FPGA VCU1287 Characterization Kit website

for the

latest XDC file.

VCU1287 Board XDC Listing

#FMC1

set_property PACKAGE_PIN AB32 [get_ports "FMC1_PRSNT_M2C_L"]

set_property IOSTANDARD LVCMOS18 [get_ports "FMC1_PRSNT_M2C_L"]

set_property PACKAGE_PIN AF32 [get_ports "FMC1_CLK0_M2C_P"]

set_property IOSTANDARD LVCMOS18 [get_ports "FMC1_CLK0_M2C_P"]

set_property PACKAGE_PIN AF33 [get_ports "FMC1_CLK0_M2C_N"]

set_property IOSTANDARD LVCMOS18 [get_ports "FMC1_CLK0_M2C_N"]

set_property PACKAGE_PIN AG31 [get_ports "FMC1_CLK1_M2C_P"]

set_property IOSTANDARD LVCMOS18 [get_ports "FMC1_CLK1_M2C_P"]

set_property PACKAGE_PIN AG32 [get_ports "FMC1_CLK1_M2C_N"]

set_property IOSTANDARD LVCMOS18 [get_ports "FMC1_CLK1_M2C_N"]

set_property PACKAGE_PIN N32 [get_ports "FMC1_CLK2_BIDIR_P"]

set_property IOSTANDARD LVCMOS18 [get_ports "FMC1_CLK2_BIDIR_P"]

set_property PACKAGE_PIN N33 [get_ports "FMC1_CLK2_BIDIR_N"]

set_property IOSTANDARD LVCMOS18 [get_ports "FMC1_CLK2_BIDIR_N"]

set_property PACKAGE_PIN P31 [get_ports "FMC1_CLK3_BIDIR_P"]

set_property IOSTANDARD LVCMOS18 [get_ports "FMC1_CLK3_BIDIR_P"]

set_property PACKAGE_PIN N31 [get_ports "FMC1_CLK3_BIDIR_N"]

set_property IOSTANDARD LVCMOS18 [get_ports "FMC1_CLK3_BIDIR_N"]

#FMC1 LA

set_property PACKAGE_PIN AD33 [get_ports "FMC1_LA00_CC_P"]

set_property IOSTANDARD LVCMOS18 [get_ports "FMC1_LA00_CC_P"]

set_property PACKAGE_PIN AE33 [get_ports "FMC1_LA00_CC_N"]

Send Feedback

Содержание Virtex UltraScale FPGA VCU1287

Страница 1: ...VCU1287 Characterization Board User Guide UG1121 v1 0 December 11 2015...

Страница 2: ...rization Board www xilinx com 2 UG1121 v1 0 December 11 2015 Revision History The following table shows the revision history for this document Date Version Revision 12 11 2015 1 0 Initial Xilinx relea...

Страница 3: ...Chapter 3 Board Component Descriptions Overview 12 Component Descriptions 12 Power Management 12 Appendix A Default Jumper Settings Introduction 56 Appendix B VITA 57 1 FMC Connector Pinouts Introduc...

Страница 4: ...x com 4 UG1121 v1 0 December 11 2015 Board EEPROM Data Menu 94 FPGA CONFIG Menu 95 Appendix E Additional Resources and Legal Notices Xilinx Resources 96 Solution Centers 96 References 96 Please Read I...

Страница 5: ...095 FFVB2104E FPGA The VCU1287 board schematic bill of material BOM layout files and reference designs are available online at the VCU1287 Characterization Kit website FPGA Compatibility The VCU1287 b...

Страница 6: ...7 QUAD 228 QUAD 229 QUAD 230 QUAD 231 UltraScale FPGA XCVU095 FFVB2104E Analog Digital Converter SYSMON FPGA Power Source On Board Regulation VCCINT 0 95V 60A VCCBRAM 0 95V 7A VCCAUX 1 8V 8A VCCO_HP 1...

Страница 7: ...lent USB JTAG programming port System controller Zynq 7000 AP SoC XC7Z010 CLG225 FPGA Two MGT power modules supporting UltraScale FPGA GTY and GTH transceiver power requirements A fixed 300 MHz 2 5V L...

Страница 8: ...to a detailed functional description of the components and board features in Chapter 3 Board Component Descriptions IMPORTANT Figure 2 1 is for visual reference only and might not reflect the current...

Страница 9: ...r 11 2015 Chapter 2 Board Setup and Configuration X Ref Target Figure 2 1 Figure 2 1 VCU1287 Characterization Board Components 11 19 26 27 28 29 20 19 38 37 23 15 14 13 30 31 32 12 19 22 19 21 17 40 2...

Страница 10: ...positions for normal board operation is provided in Appendix A Default Jumper Settings 8 J10 SD card connector back side of board A list of jumpers and switches and their required positions for norma...

Страница 11: ...uired positions for normal board operation is provided in Appendix A Default Jumper Settings 24 J1 Connector for USB to Dual UART Bridge mini B receptacle 25 J99 Active Heat Sink Power Connector 26 DS...

Страница 12: ...callout 1 Figure 2 1 For further information on UltraScale FPGAs see UltraScale Architecture and Product Overview DS890 Ref 1 Power Management 12V Input Power The VCU1287 board receives 12V main power...

Страница 13: ...e polarity protection use a power supply with a current limit set at 6A maximum CAUTION Do NOT apply 12V power to more than a single input source For example do not apply power to J73 and J27 at the s...

Страница 14: ...10A max Maxim MAX20751EKX U23 MultiPhase Master Maxim VT1697SBFXQ U118 0 95V at 20A max Maxim VT1697SBFXQ U119 0 95V at 20A max Maxim VT1697SBFXQ U120 0 95V at 20A max VCCINT VCCAUX VCCBRAM VCCO_HP V...

Страница 15: ...L controller 10A VCCO_HP 1 8V Maxim MAX15301 U95 InTune digital point of load PoL controller 2 5A VCCO_HR 1 8V Utility Maxim MAX15301 U29 InTune digital point of load PoL controller 10A UTIL_2V5 2 5V...

Страница 16: ...bitor switch is set to the ON position Table 3 2 shows a list of external power connections for the different power rails Maxim MAX15027 U25 Fixed LDO regulator VCC_1V8 1 8V CAUTION The output voltage...

Страница 17: ...board includes these PMBus connectors J21 callout 20 Figure 1 2 for use with the Maxim USB to PMBus interface dongle MAXPOWERTOOL002 Ref 5 and the InTune Digital Power GUI J4 callout 21 Figure 1 2 is...

Страница 18: ...s connector J4 This configuration is required when using Maxim power tools to monitor and control both the FPGA power rails and the transceiver power rails using the Maxim InTune digital power GUI Mor...

Страница 19: ...the VCU1287 board for evaluation The modules can be plugged into connectors J138 and J93 or J46 and J124 in the outlined and labeled power module locations shown in Figure 3 3 and Figure 3 4 Table 3...

Страница 20: ...providing external power to the MGT transceiver rails Information about the available MGT power modules included with the VCU1287 board characterization kit is available from the vendor websites Ref...

Страница 21: ...nt Descriptions The fan power connections are detailed in Table 3 4 Figure 3 6 shows the heat sink fan power connector J99 Table 3 4 Fan Power Connections Fan Wire Header Pin Black J99 1 GND Red J99 2...

Страница 22: ...mode callout 8 Figure 2 1 The FPGA can be configured from an SD memory card installed in J10 with the help of the system controller U38 which reads a predefined bit file from the SD card and configur...

Страница 23: ...U1287 board utilizes a Xilinx XC7Z010 CLG225 Zynq 7000 AP SoC U38 callout 35 Figure 2 1 system controller that can be used to Configure the FPGA using predefined selection of configuration bit files o...

Страница 24: ...ting each address are shown in Table 3 5 System Controller GPIO Pushbuttons SW5 SW6 SW10 SW11 SW12 callout 38 Figure 2 1 are active high pushbuttons connected to GPIO pins on the system controller See...

Страница 25: ...ins Transmit TX Receive RX Request to send RTS Clear to send CTS The dual UART interface connections are split between two components UART1 SCI standard interface is connected to the XCVU095 FPGA UART...

Страница 26: ...nection FPGA U1 Schematic Net Name Device U32 Pin Function Direction IOSTANDARD Pin Function Direction BA12 RTS Output LVCMOS18 UART_CTS_I_B 18 CTS Input BB12 CTS Input LVCMOS18 UART_RTS_O_B 19 RTS Ou...

Страница 27: ...o an external clock source The FPGA MRCC pins are connected to the SMA connectors as shown in Table 3 9 Table 3 8 LVDS Oscillator MRCC Connections FPGA U1 Schematic Net Name Device 42 Pin Function Dir...

Страница 28: ...3 Clock recovery Input LVDS CM_LVDS1_N 3 Clock recovery Output J33 Clock recovery Input LVDS CM_LVDS2_P 9 Clock recovery Output H33 Clock recovery Input LVDS CM_LVDS2_N 11 Clock recovery Output G26 Re...

Страница 29: ...user DIP switches to the system controller Table 3 11 User LEDs FPGA U1 Schematic Net Name Reference Designator Pin Function Direction IOSTANDARD BD14 User LED Output LVCMOS18 APP_LED1 DS19 BF15 User...

Страница 30: ...user I O pins on the FPGA as shown in Table 3 13 These switches can be used for any purpose X Ref Target Figure 3 10 Figure 3 10 User I O J95 Table 3 13 User Pushbuttons FPGA U1 Schematic Net Name Ref...

Страница 31: ...3 11 The MGT transceivers are grouped into eight sets of four TX RX lanes referred to as a GTY Quads Q124 Q131 on the right side of the board and eight TX RX lanes referred to as GTH Quads Q224 Q231...

Страница 32: ...GTY transceiver pin is shown in Table 3 14 X Ref Target Figure 3 12 Figure 3 12 MGT Connector Pad and Pinout Table 3 14 GTY Transceiver Pins U1 FPGA Pin Net Name Quad Connector Trace Length mils BC46...

Страница 33: ...40 125_TX2_P 125 J155 3000 31 AP39 125_TX3_N 125 J155 3244 309 AP38 125_TX3_P 125 J155 3244 427 AN46 126_RX0_N 126 J38 4561 993 AN45 126_RX0_P 126 J38 4562 337 AM44 126_RX1_N 126 J38 2911 304 AM43 126...

Страница 34: ...128_RX0_N 128 J39 3318 099 AE45 128_RX0_P 128 J39 3318 535 AD44 128_RX1_N 128 J39 2091 1 AD43 128_RX1_P 128 J39 2092 008 AC46 128_RX2_N 128 J39 2134 481 AC45 128_RX2_P 128 J39 2133 745 AB44 128_RX3_N...

Страница 35: ..._P 130 J141 2550 918 R46 130_RX2_N 130 J141 2199 702 R45 130_RX2_P 130 J141 2195 953 P44 130_RX3_N 130 J141 3405 875 P43 130_RX3_P 130 J141 3409 978 U41 130_TX0_N 130 J141 3153 762 U40 130_TX0_P 130 J...

Страница 36: ...4 J40 2687 895 BA1 224_RX1_N 224 J40 2268 14 BA2 224_RX1_P 224 J40 2263 637 AW3 224_RX2_N 224 J40 2373 569 AW4 224_RX2_P 224 J40 2371 689 AV1 224_RX3_N 224 J40 2920 877 AV2 224_RX3_P 224 J40 2922 567...

Страница 37: ...226_RX2_P 226 J89 2959 423 AK1 226_RX3_N 226 J89 3406 548 AK2 226_RX3_P 226 J89 3403 205 AN8 226_TX0_N 226 J89 3882 696 AN9 226_TX0_P 226 J89 3878 481 AM6 226_TX1_N 226 J89 3307 026 AM7 226_TX1_P 226...

Страница 38: ...AE8 228_TX0_N 228 J42 2695 046 AE9 228_TX0_P 228 J42 2690 838 AD6 228_TX1_N 228 J42 2548 702 AD7 228_TX1_P 228 J42 2544 475 AC8 228_TX2_N 228 J42 2521 896 AC9 228_TX2_P 228 J42 2519 007 AB6 228_TX3_N...

Страница 39: ...TX1_P 230 J43 2574 504 R8 230_TX2_N 230 J43 2851 124 R9 230_TX2_P 230 J43 2846 931 P6 230_TX3_N 230 J43 3003 18 P7 230_TX3_P 230 J43 3000 284 N3 231_RX0_N 231 J156 3378 75 N4 231_RX0_P 231 J156 3374 5...

Страница 40: ...FCLK1_P 125 J155 AR37 126_REFCLK0_N 126 J38 AR36 126_REFCLK0_P 126 J38 AN37 126_REFCLK1_N 126 J38 AN36 126_REFCLK1_P 126 J38 AL37 127_REFCLK0_N 127 J80 AL36 127_REFCLK0_P 127 J80 AJ37 127_REFCLK1_N 12...

Страница 41: ...REFCLK1_P 225 J88 AM10 226_REFCLK0_N 226 J89 AM11 226_REFCLK0_P 226 J89 AK10 226_REFCLK1_N 226 J89 AK11 226_REFCLK1_P 226 J89 AH10 227_REFCLK0_N 227 J41 AH11 227_REFCLK0_P 227 J41 AF10 227_REFCLK1_N 2...

Страница 42: ...s reference of signal names to pin coordinates The FMC1 HPC connector JA2 provides connectivity for 75 differential user defined pairs 34 LA pairs 24 HA pairs 17 HB pairs 4 differential clocks The FMC...

Страница 43: ...C1_CLK0_M2C_N H5 AG31 FMC1_CLK1_M2C_P G2 AG32 FMC1_CLK1_M2C_N G3 N32 FMC1_CLK2_BIDIR_P K4 N33 FMC1_CLK2_BIDIR_N K5 P31 FMC1_CLK3_BIDIR_P J2 N31 FMC1_CLK3_BIDIR_N J3 E36 FMC1_HA00_CC_P F4 D36 FMC1_HA00...

Страница 44: ...E38 FMC1_HA18P J18 D38 FMC1_HA18N J19 H34 FMC1_HA19P F19 G34 FMC1_HA19N F20 H36 FMC1_HA20P E18 G36 FMC1_HA20N E19 J35 FMC1_HA21P K19 J36 FMC1_HA21N K20 G37 FMC1_HA22P J21 F37 FMC1_HA22N J22 H37 FMC1_...

Страница 45: ...6 FMC1_HB11N J31 P28 FMC1_HB12P F31 N28 FMC1_HB12N F32 P29 FMC1_HB13P E30 N29 FMC1_HB13N E31 T26 FMC1_HB14P K34 R26 FMC1_HB14N K35 T27 FMC1_HB15P J33 R27 FMC1_HB15N J34 T28 FMC1_HB16P F34 R28 FMC1_HB1...

Страница 46: ...31 FMC1_LA12P G15 AH32 FMC1_LA12N G16 AF34 FMC1_LA13P D17 AG34 FMC1_LA13N D18 AH33 FMC1_LA14P C18 AJ33 FMC1_LA14N C19 AH34 FMC1_LA15P H19 AJ34 FMC1_LA15N H20 AJ31 FMC1_LA16P G18 AK31 FMC1_LA16N G19 L3...

Страница 47: ..._LA30P H34 R32 FMC1_LA30N H35 R30 FMC1_LA31P G33 P30 FMC1_LA31N G34 U30 FMC1_LA32P H37 T30 FMC1_LA32N H38 V31 FMC1_LA33P G36 U31 FMC1_LA33N G37 AB32 FMC1_PRSNT_M2C_L H2 Table 3 19 VITA 57 1 FMC2 HPC C...

Страница 48: ...09P D14 AU27 FMC2_LA09N D15 AV27 FMC2_LA10P C14 AV28 FMC2_LA10N C15 BA27 FMC2_LA11P H16 BA28 FMC2_LA11N H17 BB26 FMC2_LA12P G15 BB27 FMC2_LA12N G16 BA25 FMC2_LA13P D17 BB25 FMC2_LA13N D18 BC26 FMC2_LA...

Страница 49: ...J2 H23 FMC3_CLK3_BIDIR_N J3 G20 FMC3_HA00_CC_P F4 G19 FMC3_HA00_CC_N F5 H19 FMC3_HA01_CC_P E2 H18 FMC3_HA01_CC_N E3 B20 FMC3_HA02P K7 A20 FMC3_HA02N K8 B19 FMC3_HA03P J6 A19 FMC3_HA03N J7 D18 FMC3_HA...

Страница 50: ...C3_HA19N F20 P19 FMC3_HA20P E18 N19 FMC3_HA20N E19 M20 FMC3_HA21P K19 M19 FMC3_HA21N K20 P18 FMC3_HA22P J21 N18 FMC3_HA22N J22 N17 FMC3_HA23P K22 M17 FMC3_HA23N K23 AY35 FMC3_HB00_CC_P K25 AY36 FMC3_H...

Страница 51: ...3_HB13P E30 BC37 FMC3_HB13N E31 BD36 FMC3_HB14P K34 BE36 FMC3_HB14N K35 BD35 FMC3_HB15P J33 BE35 FMC3_HB15N J34 BC34 FMC3_HB16P F34 BD34 FMC3_HB16N F35 BA35 FMC3_HB17_CC_P K37 BB35 FMC3_HB17_CC_N K38...

Страница 52: ...FMC3_LA08N G13 E15 FMC3_LA09P D14 D15 FMC3_LA09N D15 G17 FMC3_LA10P C14 G16 FMC3_LA10N C15 F13 FMC3_LA11P H16 E13 FMC3_LA11N H17 H17 FMC3_LA12P G15 H16 FMC3_LA12N G16 J13 FMC3_LA13P D17 H13 FMC3_LA13N...

Страница 53: ...8 B22 FMC3_LA24N H29 E25 FMC3_LA25P G27 D25 FMC3_LA25N G28 D24 FMC3_LA26P D26 D23 FMC3_LA26N D27 E23 FMC3_LA27P C26 E22 FMC3_LA27N C27 G22 FMC3_LA28P H31 F22 FMC3_LA28N H32 K25 FMC3_LA29P G30 J25 FMC3...

Страница 54: ...e UltraScale Architecture System Monitor User Guide UG580 Ref 2 I2C Bus Management The I2C bus is routed through U22 an 8 channel I2C bus multiplexer NXP Semiconductor TCA9548 The I2C IDcode for the P...

Страница 55: ...J121 and J125 are used to enable or disable the bus repeaters and isolate the system controller or the UltraScale FPGA I2C bus Table 3 21 I2C Channel Assignments U22 Channel I2C Component 0 System PM...

Страница 56: ...CBRAM Upper Left OFF SW2 3 VCCAUX Upper Left OFF SW2 4 VCCO_HP Upper Left OFF SW2 5 VCCO_HR Upper Left OFF J87 MGT PMBUS CTRL Upper Left GND 2 3 J8 MGT PMBUS ISO Center Right Installed J121 DUT I2C Up...

Страница 57: ...v1 0 December 11 2015 Appendix Appendix A Default Jumper Settings SW13 4 ADDR2 Upper Right OFF SW13 5 ADDR3 Upper Right OFF Table A 1 Default Jumper Settings Cont d Reference Designator Name Board Loc...

Страница 58: ...0 December 11 2015 Appendix B VITA 57 1 FMC Connector Pinouts Introduction Figure B 1 provides a cross reference of signal names to pin coordinates for the VITA 57 1 FMC HPC connector X Ref Target Fi...

Страница 59: ...1_CLK0_M2C_P set_property IOSTANDARD LVCMOS18 get_ports FMC1_CLK0_M2C_P set_property PACKAGE_PIN AF33 get_ports FMC1_CLK0_M2C_N set_property IOSTANDARD LVCMOS18 get_ports FMC1_CLK0_M2C_N set_property...

Страница 60: ...ARD LVCMOS18 get_ports FMC1_LA07P set_property PACKAGE_PIN AA33 get_ports FMC1_LA07N set_property IOSTANDARD LVCMOS18 get_ports FMC1_LA07N set_property PACKAGE_PIN AC34 get_ports FMC1_LA08P set_proper...

Страница 61: ...PIN L33 get_ports FMC1_LA24P set_property IOSTANDARD LVCMOS18 get_ports FMC1_LA24P set_property PACKAGE_PIN K33 get_ports FMC1_LA24N set_property IOSTANDARD LVCMOS18 get_ports FMC1_LA24N set_property...

Страница 62: ..._property PACKAGE_PIN A33 get_ports FMC1_HA04N set_property IOSTANDARD LVCMOS18 get_ports FMC1_HA04N set_property PACKAGE_PIN D33 get_ports FMC1_HA05P set_property IOSTANDARD LVCMOS18 get_ports FMC1_H...

Страница 63: ...ports FMC1_HA18N set_property PACKAGE_PIN H34 get_ports FMC1_HA19P set_property IOSTANDARD LVCMOS18 get_ports FMC1_HA19P set_property PACKAGE_PIN G34 get_ports FMC1_HA19N set_property IOSTANDARD LVCMO...

Страница 64: ...N L28 get_ports FMC1_HB09P set_property IOSTANDARD LVCMOS18 get_ports FMC1_HB09P set_property PACKAGE_PIN K28 get_ports FMC1_HB09N set_property IOSTANDARD LVCMOS18 get_ports FMC1_HB09N set_property PA...

Страница 65: ..._property PACKAGE_PIN AN27 get_ports FMC2_LA03N set_property IOSTANDARD LVCMOSxx get_ports FMC2_LA03N set_property PACKAGE_PIN AN28 get_ports FMC2_LA04P set_property IOSTANDARD LVCMOSxx get_ports FMC2...

Страница 66: ...rts FMC2_LA17_CC_N set_property PACKAGE_PIN BE27 get_ports FMC2_LA18_CC_P set_property IOSTANDARD LVCMOSxx get_ports FMC2_LA18_CC_P set_property PACKAGE_PIN BF27 get_ports FMC2_LA18_CC_N set_property...

Страница 67: ...STANDARD LVCMOS18 get_ports FMC3_LA07P set_property PACKAGE_PIN C13 get_ports FMC3_LA07N set_property IOSTANDARD LVCMOS18 get_ports FMC3_LA07N set_property PACKAGE_PIN E16 get_ports FMC3_LA08P set_pro...

Страница 68: ...perty PACKAGE_PIN C26 get_ports FMC3_LA22P set_property IOSTANDARD LVCMOS18 get_ports FMC3_LA22P set_property PACKAGE_PIN B26 get_ports FMC3_LA22N set_property IOSTANDARD LVCMOS18 get_ports FMC3_LA22N...

Страница 69: ..._property PACKAGE_PIN A20 get_ports FMC3_HA02N set_property IOSTANDARD LVCMOS18 get_ports FMC3_HA02N set_property PACKAGE_PIN B19 get_ports FMC3_HA03P set_property IOSTANDARD LVCMOS18 get_ports FMC3_H...

Страница 70: ...MC3_HA16N set_property PACKAGE_PIN J20 get_ports FMC3_HA17_CC_P set_property IOSTANDARD LVCMOS18 get_ports FMC3_HA17_CC_P set_property PACKAGE_PIN J19 get_ports FMC3_HA17_CC_N set_property IOSTANDARD...

Страница 71: ...TANDARD LVCMOS18 get_ports FMC3_HB07P set_property PACKAGE_PIN AT34 get_ports FMC3_HB07N set_property IOSTANDARD LVCMOS18 get_ports FMC3_HB07N set_property PACKAGE_PIN AV33 get_ports FMC3_HB08P set_pr...

Страница 72: ...set_property IOSTANDARD LVCMOS18 get_ports FMC3_HB21N SUPERCLOCK 2 MODULE set_property PACKAGE_PIN C28 get_ports CM_RST_B set_property IOSTANDARD LVCMOS18 get_ports CM_RST_B set_property PACKAGE_PIN D...

Страница 73: ...S18 get_ports USER_SW8 PUSH BUTTONS set_property PACKAGE_PIN AN14 get_ports USER_PB1 set_property IOSTANDARD LVCMOS18 get_ports USER_PB1 set_property PACKAGE_PIN AM14 get_ports USER_PB2 set_property I...

Страница 74: ...OS18 get_ports DUT_FREQ_CLK set_property PACKAGE_PIN AN13 get_ports DUT_FREQ_DATA set_property IOSTANDARD LVCMOS18 get_ports DUT_FREQ_DATA set_property PACKAGE_PIN AP15 get_ports DUT_FREQ_BSY set_prop...

Страница 75: ...AR46 get_ports 125_RX2_N set_property PACKAGE_PIN AT38 get_ports 125_TX1_P set_property PACKAGE_PIN AT39 get_ports 125_TX1_N set_property PACKAGE_PIN AT43 get_ports 125_RX1_P set_property PACKAGE_PIN...

Страница 76: ...CKAGE_PIN AC45 get_ports 128_RX2_P set_property PACKAGE_PIN AC46 get_ports 128_RX2_N set_property PACKAGE_PIN AD38 get_ports 128_TX1_P set_property PACKAGE_PIN AD39 get_ports 128_TX1_N set_property PA...

Страница 77: ...AGE_PIN L41 get_ports 131_TX2_N set_property PACKAGE_PIN L45 get_ports 131_RX2_P set_property PACKAGE_PIN L46 get_ports 131_RX2_N set_property PACKAGE_PIN M38 get_ports 131_TX1_P set_property PACKAGE_...

Страница 78: ...y PACKAGE_PIN AL9 get_ports 226_TX2_P set_property PACKAGE_PIN AL8 get_ports 226_TX2_N set_property PACKAGE_PIN AL4 get_ports 226_RX2_P set_property PACKAGE_PIN AL3 get_ports 226_RX2_N set_property PA...

Страница 79: ...X3_P set_property PACKAGE_PIN V1 get_ports 229_RX3_N set_property PACKAGE_PIN W9 get_ports 229_TX2_P set_property PACKAGE_PIN W8 get_ports 229_TX2_N set_property PACKAGE_PIN W4 get_ports 229_RX2_P set...

Страница 80: ...K2 get_ports 231_RX3_P set_property PACKAGE_PIN K1 get_ports 231_RX3_N set_property PACKAGE_PIN L9 get_ports 231_TX2_P set_property PACKAGE_PIN L8 get_ports 231_TX2_N set_property PACKAGE_PIN L4 get_...

Страница 81: ...ation terminal connection 115200 8 N 1 using the enhanced communication port of the Silicon Labs USB to Dual UART described in USB to Dual UART Bridge The main menu lists the available options VCU1287...

Страница 82: ...5 View VCU1287 Saved Clocks in EEPROM 6 Set VCU1287 Clock Restore Options 7 Read VCU1287 Si570 Frequency 8 Read VCU1287 Si5368 Frequency 0 Return to Main Menu Clock Menu Options This section includes...

Страница 83: ...nds might elapse before the result is returned IMPORTANT Make sure J121 is set to position 2 3 DUT I2C DIS to isolate the DUT I2C signals and prevent bus contention If contention occurs the system con...

Страница 84: ...Option 5 View VCU1287 Saved Clocks in EEPROM Saved Clocks in EEPROM Si570 User Clock 200 00000000 MHz Si5328 MGT Clock 200 00000000 MHz Option 6 Set VCU1287 Clock Restore Options 1 View VCU1287 Clock...

Страница 85: ...anned continuously until stopped by a key press Table D 1 lists the voltage rails accessible through the system controller s interface to the Maxim PMBus PMBus Menu Options VCU1287 System Controller v...

Страница 86: ...uous Scan PMBUS Voltages The list of voltages shown in option 1 is displayed and updated about once per second Pressing any key displays the PMBus menu Option 3 Get VCCINT Voltage VCCINT 0 950 V Unsca...

Страница 87: ...returned values include diagnostic information Option 8 Get UTIL5V0 Voltage UTIL5V0 5 000 V Unscaled Hex MSB 0x50 LSB 0x00 The returned values include diagnostic information Option 9 Get UTIL3V3 Volta...

Страница 88: ...Option 1 Continuous Scan Voltage and Current This option lists the voltages shown in Option 1 Get PMBus Voltages and displays the average minimum and maximum current of each rail The list is updated...

Страница 89: ..._L Monitor B Select MGTVCCAUX_L Monitor 0 Return to Previous Menu Read the selected INA226 registers1 VCU1287 System Controller v1 0 RAIL INA226 Menu 1 Get SHUNT Register 2 Get BUS Register 3 Get POWE...

Страница 90: ...nt platform management interface IPMI specification used for the FMC EEPROM The VCU1287 board system controller supports the programmable clock resources on these FMC modules IMPORTANT These FMC modul...

Страница 91: ...ify the FMC module types and the FMC connecter number The subsequent examples use FMC XM107 connected to FMC1 Option 1 Set FMC XMxxx CLOCKS VCU1287 System Controller v1 0 FMC Clock Menu 1 Set FMC XM10...

Страница 92: ...37 Enter the Si570 frequency 10 810MHz 100 Freq 100 0000000000 HS_DIV 5 N1 10 DCO 5000 0 RFREQ 0x02BC7E566E The returned values include diagnostic information Option 2 Read FMC IIC EEPROM If the FMC...

Страница 93: ...DR2 ADDR1 ADDR0 of address DIP switch SW13 are monitored as well as five user pushbuttons SW5 SW6 SW10 SW11 SW12 GPIO Menu Options VCU1287 System Controller v1 0 GPIO Menu 1 Get GPIO PL Data 2 Continu...

Страница 94: ...DR2 ADDR1 ADDR0 0 0 0 0 Pushbuttons SW11 SW12 SW5 SW6 SW10 0 0 0 0 0 FMC1_PRSNT NO FMC2_PRSNT NO PMBUS_CABLE_B NO FPGA_IIC_BUSY YES PMBUS_ALERT YES Board EEPROM Data Menu The VCU1287 includes a QSPI m...

Страница 95: ...tton SW4 is pressed The system controller CONFIG menu can also be used to select the SD card bitstream CONFIG Menu Options VCU1287 System Controller v1 0 CONFIG Menu 1 Configure UltraScale FPGA from S...

Страница 96: ...es The most up to date information related to the VCU1287 board and its documentation is available on these websites VCU1287 Characterization Kit VCU1287 Characterization Kit Master Answer Record Xili...

Страница 97: ...ation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications You may not reproduce modify distribute or publicly display the Materia...

Страница 98: ...5 Hinj SnoMakrR10 DK DEV 1SDX P A DK DEV 1SDX P 0ES DK DEV 1SGX L A DK DEV 1SMC H A DK DEV 1SMX H 0ES DK DEV 1SMX H A DK DEV 4CGX150N DK DEV 5CGTD9N DK DEV 5CSXC6N DK DEV 5M570ZN DK MAXII 1270N DK SI...

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Содержание Virtex UltraScale FPGA VCU1287

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Xilinx Virtex UltraScale FPGA VCU1287, Руководство пользователя

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Содержание Virtex UltraScale FPGA VCU1287

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