VCU1287 Characterization Board
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41
UG1121 (v1.0) December 11, 2015
Chapter 3:
Board Component Descriptions
Information for each GTH transceiver clock input is shown in
Table 3-17
.
Table 3-17:
GTH Transceiver Reference Clock Inputs
U1 FPGA Pin
Net Name
Quad
Connector
AW8
224_REFCLK0_N
224
J40
AW9
224_REFCLK0_P
224
J40
AV10 224_REFCLK1_N
224
J40
AV11 224_REFCLK1_P
224
J40
AT10 225_REFCLK0_N
225
J88
AT11 225_REFCLK0_P
225
J88
AP10 225_REFCLK1_N
225
J88
AP11 225_REFCLK1_P
225
J88
AM10 226_REFCLK0_N
226
J89
AM11 226_REFCLK0_P
226
J89
AK10 226_REFCLK1_N
226
J89
AK11 226_REFCLK1_P
226
J89
AH10 227_REFCLK0_N
227
J41
AH11 227_REFCLK0_P
227
J41
AF10 227_REFCLK1_N
227
J41
AF11 227_REFCLK1_P
227
J41
AD10 228_REFCLK0_N
228
J42
AD11 228_REFCLK0_P
228
J42
AB10 228_REFCLK1_N
228
J42
AB11 228_REFCLK1_P
228
J42
Y11
229_REFCLK0_P
229
J92
Y10
229_REFCLK0_N
229
J92
V10
229_REFCLK1_N
229
J92
V11
229_REFCLK1_P
229
J92
T10
230_REFCLK0_N
230
J43
T11
230_REFCLK0_P
230
J43
P10
230_REFCLK1_N
230
J43
P11
230_REFCLK1_P
230
J43
M10
231_REFCLK0_N
231
J156
M11
231_REFCLK0_P
231
J156
K10
231_REFCLK1_N
231
J156
K11
231_REFCLK1_P
231
J156
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