VC707 Evaluation Board
UG885 (v1.2) February 1, 2013
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Revision History
The following table shows the revision history for this document.
Date
Version
Revision
03/05/12
1.0
Initial Xilinx release.
10/08/12
1.1
Chapter 1, VC707 Evaluation Board Features
: In
, notes for J37 changed to
Samtec ASP_134486_01. The board photo in
, GPGA
(U1) Bank 32 was deleted. A note was added about the user clock for
, FPGA pin AN1 changed to AM4 and pin AN2 changed to AM3. In
GTX Transceiver Clock Generation, page 37
, 25 MHz LVDS clock changed to 125 MHz
LVDS clo
title also
changed from 25 MHz to 125 MHz. In
pin AR42 changed to AT42. In
, switching regulator supply voltage UG63 for
MGTVCCAUX was updated. In
, device type PTD08D021W (V
OUT
A) power
rail voltage changed to 1.80V. In
, values for rail number 3 changed. In
Appendix C, Master UCF Listing
, the entire listing was replaced.
Regulatory and Compliance Information
now includes a link to the Declaration of
Conformity and markings for waste electrical and electronic equipment (WEEE),
restriction of hazardous substances (RoHS), and CE compliance.
02/01/13
1.2
,
Virtex-7 XC7VX485T-2FFG1761C FPGA
,
System Clock (SYSCLK_P and SYSCLK_N)
57.1 FMC2 HPC Connector (Partially Populated)
. Updated
,
Form Factor Board TI Power System Cooling
. Added
.
Replaced PTD08D021W with PTD08D210W in
. Added third paragraph to the
introduction in
Appendix C, Master UCF Listing
. Added UG483 and removed NXP
Semiconductors in
. Added second paragraph to the introduction in
Содержание VC707
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Страница 96: ...96 www xilinx com VC707 Evaluation Board UG885 v1 2 February 1 2013 Appendix E Board Specifications...