CAN FD v2.0
47
PG223 December 5, 2018
Chapter 2:
Product Specification
TB*-DW0 Register (Address 0x0108,…, 0x0150,…)
TB*-DW1-15 Register (Address 0x010C …, 0x0154,…)
Description similar to
.
Note:
Only required DW locations needs to be written as per FDF and DLC field for a given message.
TX Event FIFO Status Register
CAN FD TX Event FIFO Register Descriptions
23:16
MM
Control
N/A
Written by CPU during TX Buffer configuration. Copied into
Tx Event FIFO element for identification of TX message
status.
15:0
Reserved
N/A
N/A
Reserved. Write to this field should be 0.
Table 2-33:
TB DW0 Register
Bits
Name
Default
Value
Description
31:24 Data bytes0 [7:0]
N/A
Data Byte 0.
Data byte needs to be transmitted with CAN or CAN FD frame
based on the DLC control field.
23:16 Data bytes1 [7:0]
N/A
Data Byte 1.
Data byte needs to be transmitted with CAN or CAN FD frame
based on the DLC control field.
15:8
Data bytes2 [7:0]
N/A
Data Byte 2.
Data byte needs to be transmitted with CAN or CAN FD frame
based on the DLC control field.
7:0
Data bytes3 [7:0]
N/A
Data Byte 3.
Data byte needs to be transmitted with CAN or CAN FD frame
based on the DLC control field.
Notes:
1. Only required DW locations needs to be written as per FDF and DLC field for a given message.
Table 2-34:
CAN FD TXE Message Space
Start
Address
Name
Access
Description
0x2000
TXE FIFO TB0-ID
Read Only
0x2004
TXE FIFO TB0-DLC
Read Only
0x2008
TXE FIFO TB1-ID
Read Only
Table 2-32:
TB DLC Register
(Cont’d)
Bits
Name
Control/
Status
Default
Value
Description