Preliminary W928C73
- 18 -
Timer 0 & 1
The W928C73 has two 16-bit Timer. Each of these Timer has two 8 bit registers which form the 16 bit
counting register. For Timer 0 they are TH0, the upper 8 bits register, and TL0, the lower 8 bit register.
Similarly Timer 1 has two 8 bit registers, TH1 and TL1. The two can be configured to operate as
timers, counting machine cycles.
The timer clock is 1/4 of the system clock. The T0 and T1 inputs are sampled in every machine cycle
at C4. If the sampled value is high in one machine cycle and low in the next, then a valid high to low
transition on the pin is recognized and the count register is incremented. Since it takes two machine
cycles to recognize a negative transition on the pin, the maximum rate at which counting will take
place is 1/24 of the master clock frequency. In the "Timer" mode, the recognized negative transition on
pin T0 and T1 can cause the count register value to be updated only in the machine cycle following
the one in which the negative edge was detected.
The "Timer" function is selected by the "C/T" bit in the TMOD Special Function Register. Each Timer
has one selection bit for its own; bit 2 of TMOD selects the function for Timer 0 and bit 6 of TMOD
selects the function for Timer 1. In addition each Timer can be set to operate in any one of four
possible modes. The mode selection is done by bits M0 and M1 in the TMOD SFR.
Mode 0
In Mode 0, the timer act as a 8 bit counter with a 5 bit, divide by 32 pre-scale. In this mode we have a
13 bit timer. The 13 bit counter consists of 8 bits of THx and 5 lower bits of TLx. The upper 3 bits of
TLx are ignored.
The negative edge of the clock increments the count in the TLx register. When the fifth bit in TLx
moves from 1 to 0, then the count in the THx register is incremented. When the count in THx moves
from FFh to 00h, then the overflow flag TFx in TCON SFR is set. The counted input is enabled only if
TRx is set and either GATE = 0 or INT x = 1. When C/ T is set to 0, then it will count clock cycles,
and if C/ T is set to 1, then it will count 1 to 0 transitions on T0 (P3.4) for timer 0 and T1 (P3.5) for
timer 1. When the 13 bit count reaches 1FFFh the next count will cause it to roll-over to 0000h. The
timer overflow flag TFx of the relevant timer is set and if enabled an interrupts will occur. Note that
when used as a timer, the time-base is clock cycles/4.
System Clock
1/4
TR0 = TCON.4
(TR1 = TCON.6)
INT1 = P3.3
INT0 = P3.2
GATE = TMOD.3
(GATE = TMOD.7)
TL0
(TL1)
00
01
TH0
(TH1)
Interrrpt
TF0
(TF1)
C/T = TMOD.2
(C/T = TMOD.6)
M1, M0 = TMOD1, TMOD0
(M1, M0 = TMOD5, TMOD4)
Timer 1 functions are shown in brakets
Mode 0 and 1 of Timer 0 & 1
